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CS8420
Digital Audio Sample Rate Converter
Features
Complete IEC60958, AES3, S/PDIF, EIAJ CP1201-compatible Transceiver with Asynchronous Sample Rate Converter Flexible 3-wire Serial Digital I/O Ports 8-kHz to 108-kHz Sample Rate Range 1:3 and 3:1 Maximum Input to Output Sample Rate Ratio 128 dB Dynamic Range -117 dB THD+N at 1 kHz Excellent Performance at Almost a 1:1 Ratio Excellent Clock Jitter Rejection 24-bit I/O Words Pin and Microcontroller Read/Write Access to Channel Status and User Data Microcontroller and Stand-Alone Modes
General Description
The CS8420 is a stereo digital audio sample rate converter (SRC) with AES3-type and serial digital audio inputs, AES3-type and serial digital audio outputs, and includes comprehensive control ability via a 4-wire microcontroller port. Channel status and user data can be assembled in block-sized buffers, making read/modify/write cycles easy. Digital audio inputs and outputs may be 24, 20, or 16 bits. The input data can be completely asynchronous to the output data, with the output data being synchronous to an external system clock. The CS8420 is available in a 28-pin SOIC package in both Commercial (-10 to +70 C) and Automotive grades (-40 to +85 C). The CDB8420 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to "Ordering Information" on page 93 for ordering information. Target applications include CD-R, DAT, MD, DVD and VTR equipment, mixing consoles, digital audio transmission equipment, high-quality D/A and A/D converters, effects processors, and computer audio systems.
VA+ AGND FILT
RERR RMCK
VD+ DGND
ILRCK ISCLK SDIN
Serial Audio Input
Sample Rate Converter
Serial Audio Output
OLRCK OSCLK SDOUT
RXP Receiver RXN
Clock & Data Recovery
AES3 S/PDIF Decoder
C & U bit Data Buffer
AES3 S/PDIF Encoder
TXP Driver TXN
Misc. Control
Control Port & Registers
Output Clock Generator
H/S
RST
EMPH U TCBL SDA/ SCL/ AD1/ AD0/ INT CDOUT CCLK CDIN CS
OMCK
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2007 (All Rights Reserved)
APRIL '07 DS245F4
CS8420
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 SPECIFIED OPERATING CONDITIONS .............................................................................................. 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 PERFORMANCE SPECIFICATIONS .................................................................................................... 7 DIGITAL FILTER CHARACTERISTICS ................................................................................................. 7 DC ELECTRICAL SPECIFICATIONS .................................................................................................... 7 DIGITAL INPUT CHARACTERISTICS .................................................................................................. 8 DIGITAL INTERFACE SPECIFICATIONS ............................................................................................. 8 TRANSMITTER CHARACTERISTICS .................................................................................................. 8 SWITCHING CHARACTERISTICS ....................................................................................................... 8 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS .............................................................. 9 SWITCHING CHARACTERISTICS - CONTROL PORT - SPITM MODE ............................................. 10 SWITCHING CHARACTERISTICS - CONTROL PORT - IC(R) MODE ............................................... 11 2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12 3. GENERAL DESCRIPTION ................................................................................................................... 13 4. DATA I/O FLOW AND CLOCKING OPTIONS ..................................................................................... 14 5. SAMPLE RATE CONVERTER (SRC) .................................................................................................. 18 5.1 Dither ............................................................................................................................................. 18 5.2 SRC Locking, Varispeed and the Sample Rate Ratio Register ..................................................... 18 6. THREE-WIRE SERIAL AUDIO PORTS ............................................................................................... 19 7. AES3 TRANSMITTER AND RECEIVER .............................................................................................. 22 7.1 AES3 Receiver ............................................................................................................................... 22 7.1.1 PLL, Jitter Attenuation, and Varispeed .................................................................................. 22 7.1.2 OMCK Out On RMCK ........................................................................................................... 22 7.1.3 Error Reporting and Hold Function ........................................................................................ 22 7.1.4 Channel Status Data Handling .............................................................................................. 23 7.1.5 User Data Handling ............................................................................................................... 23 7.1.6 Non-Audio Auto Detection ..................................................................................................... 24 7.2 AES3 Transmitter ........................................................................................................................... 24 7.2.1 Transmitted Frame and Channel Status Boundary Timing ................................................... 24 7.2.2 TXN and TXP Drivers ............................................................................................................ 25 7.3 Mono Mode Operation ................................................................................................................... 25 8. AES3 TRANSMITTER AND RECEIVER .............................................................................................. 28 8.1 Sample Rate Converter ................................................................................................................. 28 8.2 Non-SRC Delay ............................................................................................................................. 29 9. CONTROL PORT DESCRIPTION AND TIMING ................................................................................. 30 9.1 SPI Mode ....................................................................................................................................... 30 9.2 IC Mode ........................................................................................................................................ 31 9.3 Interrupts ........................................................................................................................................ 31 10. CONTROL PORT REGISTER BIT DEFINITIONS ............................................................................. 32 10.1 Memory Address Pointer (MAP) .................................................................................................. 32 10.2 Miscellaneous Control 1 (01h) ..................................................................................................... 34 10.3 Miscellaneous Control 2 (02h) ..................................................................................................... 35 10.4 Data Flow Control (03h) ............................................................................................................... 36 10.5 Clock Source Control (04h) .......................................................................................................... 37 10.6 Serial Audio Input Port Data Format (05h) ................................................................................... 38 10.7 Serial Audio Output Port Data Format (06h) ................................................................................ 39 10.8 Interrupt 1 Register Status (07h) (Read Only) ............................................................................. 40 10.9 Interrupt Register 2 Status (08h) (Read Only) ............................................................................. 41 10.10 Interrupt 1 Register Mask (09h) ................................................................................................. 41 10.11 Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh) ..................................................... 41 10.12 Interrupt 2 Register Mask (0Ch) ................................................................................................. 42
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10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh) ..................................................... 42 10.14 Receiver Channel Status (0Fh) (Read Only) ............................................................................. 43 10.15 Receiver Error (10h) (Read Only) .............................................................................................. 44 10.16 Receiver Error Mask (11h) ......................................................................................................... 45 10.17 Channel Status Data Buffer Control (12h) ................................................................................. 45 10.18 User Data Buffer Control (13h) .................................................................................................. 46 10.19 Sample Rate Ratio (1Eh) (Read Only) ....................................................................................... 47 10.20 C-Bit or U-Bit Data Buffer (20h - 37h) ........................................................................................ 47 10.21 CS8420 I.D. and Version Register (7Fh) (Read Only) ............................................................... 47 11. SYSTEM AND APPLICATIONS ISSUES ........................................................................................... 48 11.1 Reset, Power Down and Start-up Options ................................................................................... 48 11.2 Transmitter Startup ...................................................................................................................... 48 11.3 SRC Invalid State ......................................................................................................................... 49 11.4 C/U Buffer Data Corruption .......................................................................................................... 49 11.5 Block-Mode U-Data D-to-E Buffer Transfers ............................................................................... 50 11.6 ID Code and Revision Code ........................................................................................................ 50 11.7 Power Supply, Grounding, and PCB layout ................................................................................. 50 11.8 Synchronization of Multiple CS8420s .......................................................................................... 50 11.9 Extended Range Sample Rate Conversion ................................................................................. 50 12. SOFTWARE MODE - PIN DESCRIPTION ......................................................................................... 51 13. HARDWARE MODES ......................................................................................................................... 55 13.1 Overall Description ....................................................................................................................... 55 13.1.1 Hardware Mode Definitions ................................................................................................. 55 13.1.2 Serial Audio Port Formats ................................................................................................... 55 13.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input) ............................................ 56 13.2.1 Pin Description - Hardware Mode 1 .................................................................................... 57 13.3 Hardware Mode 2 Description ..................................................................................................... 59 13.3.1 Pin Description - Hardware Mode 2 .................................................................................... 61 13.4 Hardware Mode 3 Description ..................................................................................................... 63 13.4.1 Pin Description - Hardware Mode 3 .................................................................................... 65 13.5 Hardware Mode 4 Description ..................................................................................................... 67 13.5.1 Pin Description - Hardware Mode 4 .................................................................................... 69 13.6 Hardware Mode 5 Description ..................................................................................................... 71 13.6.1 Pin Description - Hardware Mode 5 .................................................................................... 72 13.7 Hardware Mode 6 Description ..................................................................................................... 74 13.7.1 Pin Description - Hardware Mode 6 .................................................................................... 76 14. EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPONENTS ................ 78 14.1 AES3 Transmitter External Components ..................................................................................... 78 14.2 AES3 Receiver External Components ......................................................................................... 79 14.3 Isolating Transformer Requirements ............................................................................................ 80 15. CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT .................................................. 81 15.1 AES3 Channel Status(C) Bit Management .................................................................................. 81 15.1.1 Manually Accessing the E Buffer ......................................................................................... 82 15.1.2 Reserving the First 5 Bytes in the E Buffer ......................................................................... 83 15.1.3 Serial Copy Management System (SCMS) ......................................................................... 83 15.1.4 Channel Status Data E Buffer Access ................................................................................. 83 15.1.5 One-Byte Mode ................................................................................................................... 84 15.1.6 Two-Byte Mode ................................................................................................................... 84 15.2 AES3 User (U) Bit Management .................................................................................................. 84 15.2.1 Mode 1: Transmit All Zeros ................................................................................................. 84 15.2.2 Mode 2: Block Mode ............................................................................................................ 84 15.2.3 IEC60958 Recommended U Data Format for Consumer Applications ............................... 85 15.2.4 Mode (3): Reserved ............................................................................................................. 85 15.2.5 Mode (4): IEC Consumer B ................................................................................................. 85 DS245F4 3
CS8420
16. PLL FILTER ........................................................................................................................................ 87 16.1 General ........................................................................................................................................ 87 16.2 External Filter Components ......................................................................................................... 87 16.2.1 General ................................................................................................................................ 87 16.2.2 Capacitor Selection ............................................................................................................. 88 16.2.3 Circuit Board Layout ............................................................................................................ 88 16.3 Component Value Selection ........................................................................................................ 88 16.3.1 Identifying the Part Revision ................................................................................................ 88 16.3.2 Locking to the RXP/RXN Receiver Inputs ........................................................................... 89 16.3.3 Locking to the ILRCK Input ................................................................................................. 89 16.3.4 Jitter Tolerance .................................................................................................................... 90 16.3.5 Jitter Attenuation ................................................................................................................. 90 17. PARAMETER DEFINITIONS .............................................................................................................. 91 18. PACKAGE DIMENSIONS .................................................................................................................. 92 THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................................. 92 19. ORDERING INFORMATION .............................................................................................................. 93 20. REVISION HISTORY .......................................................................................................................... 93
LIST OF FIGURES
Figure 1.Audio Port Master Mode Timing ................................................................................................... 9 Figure 2.Audio Port Slave Mode and Data Input Timing ............................................................................. 9 Figure 3.SPI Mode Timing ........................................................................................................................ 10 Figure 4.IC Mode Timing ......................................................................................................................... 11 Figure 5.Recommended Connection Diagram for Software Mode ........................................................... 12 Figure 6.Software Mode Audio Data Flow Switching Options ................................................................... 14 Figure 7.CS8420 Clock Routing ................................................................................................................ 14 Figure 8.Serial Audio Input, using PLL, SRC Enabled .............................................................................. 16 Figure 9.Serial Audio Input, No PLL, SRC Enabled .................................................................................. 16 Figure 10.AES3 Input, SRC Enabled ........................................................................................................ 16 Figure 11.Serial Audio Input, AES3 Input Clock Source, SRC Enabled ................................................... 16 Figure 12.Serial Audio Input, SRC Output Clocked by AES3 Recovered Clock ....................................... 16 Figure 13.AES3 Input, SRC to Serial Audio Output, Serial Audio Input to AES3 Out ............................... 16 Figure 14.AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out, No SRC ......................... 17 Figure 15.AES3 Input to Serial Audio Output Only ................................................................................... 17 Figure 16.Input Serial Port to AES3 Transmitter ....................................................................................... 17 Figure 17.Serial Audio Input Example Formats ........................................................................................ 20 Figure 18.Serial Audio Output Example Formats ...................................................................................... 21 Figure 19.AES3 Receiver Timing for C & U Pin Output Data ................................................................... 23 Figure 20.AES3 Transmitter Timing for C, U and V Pin Input Data .......................................................... 26 Figure 21.Mono Mode Operation Compared to Normal Stereo Operation ............................................... 27 Figure 22.Control Port Timing in SPI Mode .............................................................................................. 30 Figure 23.Control Port Timing in IC Mode ............................................................................................... 31 Figure 24.Hardware Mode 1 - Default Data Flow, AES3 Input ................................................................. 56 Figure 25.Hardware Mode 2 - Default Data Flow, Serial Audio Input ....................................................... 59 Figure 26.Hardware Mode 3 - Transceive Data Flow, with SRC .............................................................. 63 Figure 27.Hardware Mode 4 - Transceive Data Flow, Without SRC ......................................................... 67 Figure 28.Hardware Mode 5 - AES3 Receiver Only ................................................................................. 71 Figure 29.Hardware Mode 6 - AES3 Transmitter Only ............................................................................. 74 Figure 30.Professional Output Circuit ....................................................................................................... 78 Figure 31.Consumer Output Circuit .......................................................................................................... 78 Figure 32.TTL/CMOS Output Circuit ......................................................................................................... 79 Figure 33.Professional Input Circuit .......................................................................................................... 79 Figure 34.Transformerless Professional Input Circuit ............................................................................... 79 4 DS245F4
CS8420
Figure 35.Consumer Input Circuit ............................................................................................................. 80 Figure 36.TTL/CMOS Input Circuit ............................................................................................................ 80 Figure 37.Channel Status Data Buffer Structure ....................................................................................... 81 Figure 38.Channel Status Block Handling When Fso is Not Equal to Fsi ................................................. 82 Figure 39.Flowchart for Reading the E Buffer ........................................................................................... 82 Figure 40.Flowchart for Writing the E Buffer ............................................................................................. 83 Figure 41.PLL Block Diagram ................................................................................................................... 87 Figure 42.Recommended Layout Example ............................................................................................... 88 Figure 43.Jitter Tolerance Template ......................................................................................................... 90 Figure 44.Revision D Jitter Attenuation ..................................................................................................... 90 Figure 45.Revision D1 Jitter Attenuation ................................................................................................... 90
LIST OF TABLES
Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN ...................... 28 Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK ........................... 28 Table 3. Non-SRC Delay ........................................................................................................................... 29 Table 4. Summary of all Bits in the Control Register Map ........................................................................ 33 Table 5. Hardware Mode Definitions ......................................................................................................... 55 Table 6. Serial Audio Output Formats Available in Hardware Mode ......................................................... 55 Table 7. Serial Audio Input Formats Available in Hardware Mode ............................................................ 55 Table 8. Hardware Mode 1 Start-Up Options ............................................................................................ 56 Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function ...................................................................... 60 Table 10. HW Mode 2 Serial Audio Port Format Selection ....................................................................... 60 Table 11. Hardware Mode 2 Start-Up Options .......................................................................................... 60 Table 12. Hardware Mode 3 Start-Up Options .......................................................................................... 64 Table 13. Hardware Mode 4 Start-Up Options .......................................................................................... 68 Table 14. Hardware Mode 5 Start-Up Options .......................................................................................... 71 Table 15. HW 6 COPY/C and ORIG Pin Function .................................................................................... 75 Table 16. HW 6 Serial Port Format Selection ........................................................................................... 75 Table 17. Second Line Part Marking ......................................................................................................... 88 Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz ................................................................................... 89 Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz* ................................................................................ 89 Table 20. Locking to the ILRCK Input ....................................................................................................... 89
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CS8420 1. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25C.
SPECIFIED OPERATING CONDITIONS
AGND, DGND = 0 V, all voltages with respect to 0 V. Parameter Power Supply Voltage Ambient Operating Temperature: Commercial Grade Automotive Grade Symbol VD+, VA+ TA Min 4.75 -10 -40 Typ 5.0 Max 5.25 +70 +85 Units V C C
ABSOLUTE MAXIMUM RATINGS
AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Power Supply Voltage Input Current, Any Pin Except Supplies, RXP/RXN (Note 1) Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up. Symbol VD+, VA+ Iin Vin TA Tstg Min -0.3 -55 -65 Max 6.0 10 (VD+) + 0.3 125 150 Units V mA V C C
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CS8420 PERFORMANCE SPECIFICATIONS
Parameter* Dynamic Range Input Sample Rate Output Sample Rate Output to Input Sample Rate Ratio Total Harmonic Distortion + Noise 1 kHz, -1 dBFS, 0.33 < Fso/Fsi < 1.7 1 kHz, -1 dBFS, 0.33 < Fso/Fsi < 3 10 kHz, -1 dBFS, 0.33 < Fso/Fsi < 1.7 10 kHz, -1 dBFS, 0.33 < Fso/Fsi < 3 Peak idle channel noise component Resolution Gain Error THD+N 16 -0.12 -117 -112 -110 -107 -140 24 0 dB dB dB dB dBFS bits dB (serial input port) Fsi Fso Symbol Min 120 8 8 0.33 Typ 128 Max 108 108 3 Units dB kHz kHz
DIGITAL FILTER CHARACTERISTICS
Parameter* Passband Passband Ripple Stopband (Downsampling) Stopband Attenuation Group Delay Group Delay Variation vs. Frequency Interchannel Phase Deviation 2. See "AES3 Transmitter and Receiver" on page 28. (Note 2) tgd tgd Upsampling Downsampling Symbol Min 0 0 0.5465*Fso 110 Typ Max 0.4535*Fsi 0.4535*Fso 0.007 Fsi/2 1.75 0.0 0.0 Units Hz Hz dB Hz dB ms s
DC ELECTRICAL SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V. Parameters Power Down Mode (Note 3) Supply Current in power down Normal Operation (Note 4) Supply Current at 48 kHz Fso and Fsi Supply Current at 96 kHz Fso and Fsi VA+ VD+ VA+ VD+ 3.7 66 7.0 125 mA mA mA mA VA+ VD+ 20 20 A A Symbol Min Typ Max Units
3. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 4. Normal operation is defined as RST = HI.
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CS8420 DIGITAL INPUT CHARACTERISTICS
Parameters Input Leakage Current Differential Input Voltage, RXP to RXN Symbol Iin VTH Min 200 Typ 10 Max 15 Units A mVpp
DIGITAL INTERFACE SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V. Parameters High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN Low-Level Output Voltage (IOH = 3.2 mA), except TXP/TXN High-Level Output Voltage (IOH = -21 mA), TXP, TXN Low-Level Output Voltage (IOH = 21 mA), TXP, TXN High-Level Input Voltage, except RXP, RXN Low-Level Input Voltage, except RXP, RXN VIH VIL Symbol VOH VOL Min (VD+) - 1.0 (VD+) - 0.7 2.0 -0.3 Max 0.4 0.7 (VD+) + 0.3 0.8 Units V V V V V V
TRANSMITTER CHARACTERISTICS
Parameters TXP Output Resistance TXN Output Resistance Symbol RTXP RTXN Typ 25 25 Units
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF. Parameter RST pin Low Pulse Width OMCK Frequency for OMCK = 512 * Fso OMCK Low and High Width for OMCK = 512 * Fso OMCK Frequency for OMCK = 384 * Fso OMCK Low and High Width for OMCK = 384 * Fso OMCK Frequency for OMCK = 256 * Fso OMCK Low and High Width for OMCK = 256 * Fso PLL Clock Recovery Sample Rate Range RMCK output jitter RMCK output duty cycle RMCK Input Frequency RMCK Input Low and High Width AES3 Transmitter Output Jitter 5. Cycle-to-cycle jitter using 32-96 kHz external PLL components. 6. PLL is bypassed (RXD1:0 bits in the Clock Source Control register set to 10b), clock is input to the RMCK pin. 8 DS245F4 (Note 6) (Note 6) (Note 5) Symbol Min 200 4.096 8.2 3.072 12.3 2.048 16.4 8.0 40 2.048 16.4 Typ 200 50 Max 55.3 41.5 27.7 108.0 60 27.7 1 Units s MHz ns MHz ns MHz ns kHz ps RMS % MHz ns ns
CS8420 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF. Parameter OSCLK Active Edge to SDOUT Output Valid SDIN Setup Time Before ISCLK Active Edge SDIN Hold Time After ISCLK Active Edge Master Mode O/RMCK to I/OSCLK active edge delay O/RMCK to I/OLRCK delay I/OSCLK and I/OLRCK Duty Cycle Slave Mode I/OSCLK Period I/OSCLK Input Low Width I/OSCLK Input High Width I/OSCLK Active Edge to I/OLRCK Edge (Note 7, 9, 11) I/OLRCK Edge Setup Before I/OSCLK Active Edge (Note 7, 9, 12) tlrcks 20 ns (Note 10) tsckw tsckl tsckh tlrckd 36 14 14 20 ns ns ns ns (Note 7, 8) (Note 9) tsmd tlmd 0 0 50 16 17 ns ns % (Note 7) (Note 7) (Note 7) Symbol tdpd tds tdh Min 20 20 Typ Max 25 Units ns ns ns
7. The active edges of ISCLK and OSCLK are programmable. 8. When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising edge. When these signals are derived from RMCK, they are clocked from its falling edge. 9. The polarity of ILRCK and OLRCK is programmable. 10. No more than 128 SCLK per frame. 11. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK has changed. 12. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed.
ISCLK OSCLK (output) ILRCK O LRCK (output) t sm d t RM CK (output) Hardware M ode RM CK (output) Software M ode O M CK (input) lm d
ILRCK OLRCK (input) ISCLK OSCLK (input)
t lrckd
t lrcks
t sckh
t sckl
t sckw
SDIN
t ds
SDOUT
t dh
t dpd
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing
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CS8420 SWITCHING CHARACTERISTICS - CONTROL PORT - SPITM MODE
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF. Parameter CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 15) (Note 15) (Note 14) (Note 13) Symbol fsck tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2 Min 0 1.0 20 66 66 40 18 Typ Max 6.0 45 25 25 100 100 Units MHz s ns ns ns ns ns ns ns ns ns ns
13. If Fso or Fsi is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fso and less than 128 Fsi. This is dictated by the timing requirements necessary to access the Channel Status and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should be safe for all possible conditions. 14. Data must be held for sufficient time to bridge the transition time of CCLK. 15. For fsck < 1 MHz.
CS t css CCLK t r2 CDIN t dsu t dh t f2 t scl t sch t csh
t pd
CDOUT
Figure 3. SPI Mode Timing
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CS8420 SWITCHING CHARACTERISTICS - CONTROL PORT - IC(R) MODE
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF. Parameter SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup Time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition (Note 16) Symbol fscl tbuf thdst tlow thigh tsust thdd tsud tr tf tsusp Min 4.7 4.0 4.7 4.0 4.7 0 250 4.7 Typ Max 100 25 25 Units kHz s s s s s s ns ns ns s
16. Data must be held for sufficient time to bridge the 25 ns transition time of SCL.
Stop SDA t buf SCL
Start
Repeated Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 4. IC Mode Timing
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CS8420 2. TYPICAL CONNECTION DIAGRAM
+5V Analog Supply *
Ferrite * Bead 0.1F 0.1F
+5V Digital Supply
VA+ AES3/ SPDIF Source Cable Termination RXP RXN CS8420 3-wire Serial Audio Source ILRCK ISCLK SDIN RMCK OMCK
VD+ TXP TXN Cable Interface AES3/ SPDIF Equipment
OLRCK OSCLK SDOUT
3-wire Serial Audio Input Device
Clock Source and Control
47k Hardware Control
SDA/CDOUT AD0 / CS SCL/CCLK AD1/CDIN INT EMPH / AD2 U RERR RST TCBL H/S AGND FILT DGND RFILT CFILT CRIP
Microcontroller
To other CS8420's
* A separate analog supply is only necessary in applications where RMCK is used for a jitter sensitive task. For applications where RMCK is not used for a jitter sensitive task, connect VA+ to VD+ via a ferrite bead. Keep the decoupling capacitor between VA+ and AGND.
Figure 5. Recommended Connection Diagram for Software Mode
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CS8420 3. GENERAL DESCRIPTION
The CS8420 is a fully asynchronous sample rate converter plus AES3 transceiver intended to be used in digital audio systems. Such systems include digital mixing consoles, effects processors, tape recorders, and computer multimedia systems. The CS8420 is intended for 16-, 20-, and 24-bit applications where the input sample rate is unknown, or is known to be asynchronous to the system sample rate. On the input side of the CS8420, AES3 or 3-wire serial format can be chosen. The output side produces both AES3 and 3-wire serial format. An IC/SPI-compatible microcontroller interface allows full block processing of channel status and user data via block reads from the incoming AES3 data stream and block writes to the outgoing AES3 data stream. The user can also access information decoded from the input AES3 data stream, such as the presence of non-audio data and pre-emphasis, as well as control the various modes of the device. For users who prefer not to use a micro-controller, six hardware modes have been provided and documented towards the end of this data sheet. In these modes, flexibility is limited, with pins providing some programmability. When used for AES3-input/AES3-output applications, the CS8420 can automatically transceive user data that conforms to the IEC60958-recommended format. The CS8420 also allows access to the relevant bits in the AES3 data stream to comply with the serial copy management system (SCMS). The diagram on the cover of this data sheet shows the main functional blocks of the CS8420. Figure 5 shows the supply and external connections to the device. Familiarity with the AES3 and IEC60958 specifications are assumed throughout this document. Application Note 22: Overview of Digital Audio Interface Data Structures, contains a tutorial on digital audio specifications. The paper An Understanding and Implementation of the SCMS Serial Copy Management System for Digital Audio Transmission, by Clif Sanchez, is an excellent tutorial on SCMS. It may be obtained from Cirrus Logic, Inc., or from the AES. To guarantee system compliance, the proper standards documents should be obtained. The latest AES3 standard should be obtained from the Audio Engineering Society (ANSI), the latest IEC60958 standard from the International Electrotechnical Commission and the latest EIAJ CP-1201 standard from the Japanese Electronics Bureau.
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CS8420 4. DATA I/O FLOW AND CLOCKING OPTIONS
The CS8420 can be configured for nine connectivity alternatives, referred to as data flows. Each data flow has an associated clocking set-up. Figure 6 shows the data flow switching, along with the control register bits which control the switches. This drawing only shows the audio data paths for simplicity. Figure 7 shows the internal clock routing and the associated control register bits. The clock routing constraints determine which data routing options are actually usable.
SPD1-0 ILRCK ISCLK SDIN Serial Audio Input SRCD Sample Rate Converter AES3 Receiver TXD1-0 AES3 Encoder Serial Audio Output AESBP TXOFF TXP TXN OLRCK OSCLK SDOUT
RXN RXP
Figure 6. Software Mode Audio Data Flow Switching Options
SDIN ISCLK ILRCK
SERIAL AUDIO INPUT RXD0
0
SIMS
SAMPLE RATE CONVERTER
SERIAL AUDIO OUTPUT
SDOUT OSCLK OLRCK
RMCKF
1
MUX
0
INC CHANNEL STATUS MEMORY TXN AES3 TRANSMIT TXP
MUX RXP
1
PLL
/
1
0
USER BIT SWCLK UNLOCK MEMORY
MUX
MUX
0 1 0
OUTC
MUX RMCK
1
/
RXD1 CLK[1:0]
OMCK
*Note: When SWCLK mode is enabled, signal input on OMCK is only output through RMCK and not routed back through the RXD1 multiplexer; RMCK is not bi-directional in this mode.
Figure 7. CS8420 Clock Routing
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CS8420
The AESBP switch allows a TTL level, bi-phase mark-encoded data stream connected to RXP to be routed to the TXP and TXN pin drivers. The TXOFF switch causes the TXP and TXN outputs to be driven to ground In modes including the SRC function, there are two audio-data-related clock domains. One domain includes the input side of SRC, plus the attached data source. The second domain includes the output side of the SRC, plus any attached output ports. There are two possible clock sources. The first known as the recovered clock, is the output of a PLL, and is connected to the RCMK pin. The input to the PLL can be either the incoming AES3 data stream or the ILRCK word rate clock from the serial audio input port. The second clock is input via the OMCK pin, and would normally be a crystalderived stable clock. The Clock Source Control Register bits determine which clock is connected to which domain. By studying the following drawings, and appropriately setting the Data Flow Control and Clock Source Control register bits, the CS8420 can be configured to fit a variety of application requirements. The following drawings illustrate the possible valid data flows. The audio data flow is indicated by the thin lines; the clock routing is indicated by the bold lines. The register settings for the Data Flow Control register and the Clock Source Register are also shown for each data flow. Some of the register settings may appear to be not relevant to the particular data flow in question, but have been assigned a particular state. This is done to minimize power consumption. The AESBP data path from the RXP pin to the AES3 output drivers, and the TXOFF control, have been omitted for clarity, but are present and functional in all modes where the AES3 transmitter is in use. Figures 8 and 9 show audio data entering via the serial audio input port, then passing through the sample rate converter, and then output both to the serial audio output port and to the AES3 transmitter. Figure 8 shows the PLL recovering the input clock from ILRCK word clock. Figure 9 shows using a direct 256*Fsi clock input via the RMCK pin, instead of the PLL. Figure 10 shows audio data entering via the AES3 Receiver. The PLL locks onto the pre-ambles in the incoming audio stream, and generates a 256*Fsi clock. The rate-converted data is then output via the serial audio output port and via the AES3 transmitter. Figure 11 shows the same data flow as Figure 8. The input clock is derived from an incoming AES3 data stream. The incoming data must be synchronous to the AES3 data stream. Figure 12 shows the same data flow as Figure 8. The input data must be synchronous to OMCK. The output data is clocked by the recovered PLL clock from an AES3 input stream. This may be used to implement a "house sync" architecture. Figure 8 shows audio data entering via the AES3 receiver, passing through the sample rate converter, and then exiting via the serial audio output port. Synchronous audio data may then be input via the serial audio input port and output via the AES3 transmitter. Figure 14 is the same as Figure 13, but without the sample rate converter. The whole data path is clocked via the PLL generated recovered clock. Figure 15 illustrates a standard AES3 receiver function, with no rate conversion. Figure 16 shows a standard AES3 transmitter function, with no rate conversion.
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CS8420
Serial Audio Output SDIN ISCLK ILRCK Serial Audio Input PLL Sample Rate Converter
OLRCK OSCLK SDOUT
Serial Audio Output SDIN ISCLK ILRCK Serial Audio Input Sample Rate Converter
OLRCK OSCLK SDOUT
AES3 Encoder & Driver
TXP TXN
AES3 Encoder & Driver
TXP TXN
RMCK Data Flow Control Bits TXD1-0: 00 SPD1-0: 00 SRCD: 0
OMCK Clock Source Control Bits OUTC: 0 INC: 0 RXD1-0: 00
RMCK Data Flow Control Bits TXD1-0: 00 SPD1-0: 00 SRCD: 0
OMCK Clock Source Control Bits OUTC: 0 INC: 0 RXD1-0: 10
Figure 8. Serial Audio Input, using PLL, SRC Enabled
Figure 9. Serial Audio Input, No PLL, SRC Enabled
Serial Audio Output RXN RXP AES3 Rx & Decode PLL Sample Rate Converter
OLRCK OSCLK SDOUT
Serial Audio Output SDIN ISCLK ILRCK RXN Serial Audio Input AES3 Rx Sample Rate Converter
OLRCK OSCLK SDOUT
AES3 Encoder & Driver
TXP TXN
AES3 Encoder & Driver
TXP TXN
RXP RMCK Data Flow Control Bits TXD1-0: 00 SPD1-0: 00 SRCD: 1 OMCK Clock Source Control Bits OUTC: 0 0 INC: RXD1-0: 01
PLL RMCK OMCK
Data Flow Control Bits TXD1-0: 00 SPD1-0: 00 SRCD: 0
Clock Source Control Bits OUTC: 0 INC: 0 RXD1-0: 01
Figure 10. AES3 Input, SRC Enabled
Figure 11. Serial Audio Input, AES3 Input Clock Source,
SDOUT OSCLK OLRCK SDIN ISCLK ILRCK
SDIN ISCLK ILRCK
Serial Audio Input
Sample Rate Converter PLL AES3 Rx
Serial Audio Output
OLRCK OSCLK SDOUT
Serial Serial Audio Audio Output Input RXN RXP AES3 Sample Rx & Rate Decode Converter PLL AES3 Encoder & Driver TXP TXN
AES3 Encoder & Driver
TXP TXN
OMCK
RXP RXN
RMCK
RMCK Data Flow Control Bits TXD1-0: 01 SPD1-0: 00 SRCD: 1
OMCK Clock Source Control Bits OUTC: 0 INC: 0 RXD1-0: 01
Data Flow Control Bits TXD1-0: 00 SPD1-0: 00 SRCD: 0
Clock Source Control Bits OUTC: 1 INC: 1 RXD1-0: 01
Figure 12. Serial Audio Input, SRC Output Clocked by AES3 Recovered Clock
Figure 13. AES3 Input, SRC to Serial Audio Output, Serial Audio Input to AES3 Out
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CS8420
SDOUT OSCLK OLRCK SDIN ISCLK ILRCK
Serial Serial Audio Audio Output Input RXN RXP AES3 Rx & Decode PLL AES3 Encoder & Driver TXP
RXN RXP
AES3 Rx & Decode PLL
Serial Audio Output
OLRCK OSCLK SDOUT
TXN
RMCK
RMCK Data Flow Control Bits TXD1-0: 01 SPD1-0: 10 SRCD: 0 Clock Source Control Bits OUTC: 1 INC: 0 RXD1-0: 01
Data Flow Control Bits TXD1-0: 10 SPD1-0: 10 SRCD: 0 TXOFF: 1
Clock Source Control Bits OUTC: 1 INC: 0 RXD1-0: 01
Figure 14. AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out, No SRC
Figure 15. AES3 Input to Serial Audio Output Only
SDIN ISCLK ILRCK
Serial Audio Input
AES3 Encoder & Driver
TXP TXN
OMCK Data Flow Control Bits TXD1-0: 01 SPD1-0: 01 SRCD: 0 Clock Source Control Bits OUTC: 0 INC: 1 RXD1-0: 00
Figure 16. Input Serial Port to AES3 Transmitter
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CS8420 5. SAMPLE RATE CONVERTER (SRC)
Multirate digital signal processing techniques are used to conceptually upsample the incoming data to very high rate and then downsample to the outgoing rate, resulting in a 24-bit output, regardless of the width of the input. The filtering is designed so that a full input audio bandwidth of 20 kHz is preserved if the input sample and output sample rates are greater than 44.1 kHz. When the output sample rate becomes less than the input sample rate, the input is automatically band limited to avoid aliasing products in the output. Careful design ensures minimum ripple and distortion products are added to the incoming signal. The SRC also determines the ratio between the incoming and outgoing sample rates, and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has little impact on the dynamic performance of the rate converter and has no influence on the output clock.
5.1
Dither
When using the AES3 input, and when using the serial audio input port in Left-Justified and IS modes, all input data is treated as 24 bits wide. Any truncation that has been done prior to the CS8420 to less than 24 bits should have been done using an appropriate dither process. If the serial audio input port is used to feed the SRC, and the port is in Right-Justified mode, then the input data will be truncated to the SIRES bit setting value. If SIRES bits are set to 16 or 20 bits, and the input data is 24 bits wide, truncation distortion will occur. Similarly, in any serial audio input port mode, if an inadequate number of bit clocks are entered (say 16 instead of 20), the input words will be truncated, causing truncation distortion at low levels. In summary, there is no dithering mechanism on the input side of the CS8420, and care must be taken to ensure that no truncation occurs. Dithering is used internally where appropriate inside the SRC block. The output side of the SRC can be set to 16, 20, or 24 bits. Optional dithering can be applied, and is automatically scaled to the selected output word length. This dither is not correlated between left and right channels. It is recommended that the dither control bit be left in its default ON state.
5.2
SRC Locking, Varispeed and the Sample Rate Ratio Register
The SRC calculates the ratio between the input sample rate and the output sample rate and uses this information to set up various parameters inside the SRC block. The SRC takes some time to make this calculation. For a worst case 3:1 to 1:3 input sample rate transition, the SRC will take 9400/Fso to settle (195 ms at Fso of 48 kHz). For a power-up situation, the SRC will start from 1:1; the worst case time becomes 8300/Fso (172 ms at Fso of 48 kHz). If the PLL is in use (either AES3 or serial input port), the worst case locking time for the PLL and the SRC is the sum of each locking time. If Fsi is changing, for example in a varispeed application, the REUNLOCK interrupt will occur, and the SRC will track the incoming sample rate. During this tracking mode, the SRC will still rate convert the audio data, but at increased distortion levels. Once the incoming sample rate is stable, the REUNLOCK interrupt will become false, and the SRC will return to normal levels of audio quality. The VFIFO interrupt occurs if the data buffer in the SRC overflows, which can occur if the input sample rate changes at >10%/second. Varispeed at Fsi slew rates approaching 10%/sec is only supported when the input is via the serial audio input port. When using the AES3 input, high frame rate slew rates will cause the PLL to lose lock. The sample rate ratio is also made available as a register, accessible via the control port. The upper 2 bits of this register form the integer part of the ratio, while the lower 6 bits form the fractional part. Since, in many instances Fso is known, this allows the calculation of the incoming sample rate by the host microcontroller.
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CS8420 6. THREE-WIRE SERIAL AUDIO PORTS
A 3-wire serial audio input port and a 3-wire serial audio output port is provided. Each port can be adjusted to suit the attached device via control registers. The following parameters are adjustable: master or slave, serial clock frequency, audio data resolution, left or right justification of the data relative to left/right clock, optional 1-bit cell delay of the 1st data bit, the polarity of the bit clock and the polarity of the left/right clock. By setting the appropriate control bits, many formats are possible. Figure 17 shows a selection of common input formats, along with the control bit settings. The clocking of the input section of the CS8420 may be derived from the incoming ILRCK word rate clock, using the on-chip PLL. The PLL operation is described in the AES receiver description on page 22. In the case of use with the serial audio input port, the PLL locks onto the leading edges of the ILRCK clock. Figure 18 shows a selection of common output formats, along with the control bit settings. A special AES3 direct output format is included, which allows serial output port access to the V, U, and C bits embedded in the serial audio data stream. The P bit is replaced by a bit indicating the location of the start of a block. This format is only available when the serial audio output port is being clocked by the AES3 receiver-recovered clock. Also, the received-channel status block start signal is only available in Hardware mode 5, as the RCBL pin. In Master mode, the left/right clock and the serial bit clock are outputs, derived from the appropriate clock domain master clock. In Slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the appropriate master clock, but the serial bit clock can be asynchronous and discontinuous if required. By appropriate phasing of the left/right clock and control of the serial clocks, multiple CS8420's can share one serial port. The left/right clock should be continuous, but the duty cycle does not have to be 50%, provided that enough serial clocks are present in each phase to clock all the data bits. When in Slave mode, the serial audio output port must be set to left-justified or IS data. When using the serial audio output port in Slave mode with an OLRCK input which is asynchronous to the port's data source, then an interrupt bit is provided to indicate when repeated or dropped samples occur. The CS8420 allows immediate mute of the serial audio output port audio data via a control register bit.
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CS8420
ILRCK
Left Justified (In)
Channel A Channel B
ISCLK SDIN
MSB LSB MSB LSB MSB
ILRCK
IS (In)
Channel A
Channel B
ISCLK SDIN
MSB LSB MSB LSB MSB
ILRCK
Right Justified (In)
Channel A
Channel B
ISCLK SDIN
MSB LSB MSB LSB
SIMS Left-Justified IS X X
SISF X X
SIRES1/0 00 00+
SIJUST 0 0
SIDEL 0 1 0
SISPOL 0 0 0
SILRPOL 0 1 0
Right-Justified X X XX* 1 X = don't care to match format, but does need to be set to the desired setting
+ IS can accept an arbitrary number of bits, determined by the number of ISCLK cycles * not 11 - See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 17. Serial Audio Input Example Formats
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CS8420
OLRCK Left Justified OSCLK (Out) SDOUT
Channel A
Channel B
MSB
LSB
MSB
LSB
MSB
OLRCK
IS (Out)
Channel A
Channel B
OSCLK SDOUT
MSB LSB MSB LSB MSB
OLRCK Right Justified OSCLK (Out) SDOUT
Channel A
Channel B
MSB Extended
MSB
LSB
MSB Extended
MSB
LSB
AES3 Direct (Out)
OLRCK OSCLK SDOUT
LSB
Channel A
Channel B
Channel A
Channel B
MSB V U C
LSB
MSB V U C
LSB
MSB V U C Z
LSB
MSB V U C Z
Frame 191
Frame 0
SOMS Left-Justified IS Right-Justified AES3 Direct X X 1 X
SOSF X X X X
SORES1/0 XX* XX* XX* 11
SOJUST 0 0 1 0
SODEL 0 1 0 0
SOSPOL 0 0 0 0
SOLRPOL 0 1 0 0
X = don't care to match format, but does need to be set to the desired setting * not 11 - See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 18. Serial Audio Output Example Formats
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CS8420 7. AES3 TRANSMITTER AND RECEIVER
The CS8420 includes an AES3-type digital audio receiver and an AES3-type digital audio transmitter. A comprehensive buffering scheme provides read/write access to the channel status and user data. This buffering scheme is described in "Channel Status and User Data Buffer Management" on page 81.
7.1
AES3 Receiver
The AES3 receiver accepts and decodes audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The receiver consists of a differential input stage, accessed via pins RXP and RXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from the channel status and user data. External components are used to terminate and isolate the incoming data cables from the CS8420. These components are detailed in "External AES3/SPDIF/IEC60958 Transmitter and Receiver Components" on page 78.
7.1.1
PLL, Jitter Attenuation, and Varispeed
Please see "PLL Filter" on page 87 for general description of the PLL, selection of recommended PLL filter components, and layout considerations. Figure 5 shows the recommended configuration of the two capacitors and one resistor that comprise the PLL filter.
7.1.2
OMCK Out On RMCK
A special mode is available that allows the clock that is being input through the OMCK pin to be output through the RMCK pin. This feature is controlled by the SWCLK bit in register 4 of the control registers. When the PLL loses lock, the frequency of the VCO drops to 300 kHz. The SWCLK function allows the clock from RMCK to be used as a clock in the system without any disruption when input is removed from the Receiver.
7.1.3
Error Reporting and Hold Function
While decoding the incoming AES3 data stream, the CS8420 can identify several kinds of error, indicated in the Receiver Error register. The UNLOCK bit indicates whether the PLL is locked to the incoming AES3 data. The V bit reflects the current validity bit status. The CONF (confidence) bit indicates the amplitude of the eye pattern opening, indicating a link that is close to generating errors. The BIP (bi-phase) error bit indicates an error in incoming bi-phase coding. The PAR (parity) bit indicates a received parity error. The error bits are "sticky" - they are set on the first occurrence of the associated error and will remain set until the user reads the register via the control port. This enables the register to log all unmasked errors that occurred since the last time the register was read. The Receiver Error Mask register allows masking of individual errors. The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will be reported in the receiver error register, will affect the RERR pin, will invoke the occurrence of a RERR interrupt, and will affect the current audio sample according to the status of the HOLD bits. The HOLD bits allow a choice of holding the previous sample, replacing the current sample with zero (mute), or do not change the current audio sample. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not be reported in the receiver error register, will not induce a pulse on RERR or generate a RERR interrupt, and will not affect the current audio sample. The QCRC and CCRC errors do not affect the current audio sample, even if unmasked.
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CS8420
7.1.4 Channel Status Data Handling
The first 2 bytes of the Channel Status block are decoded into the Receiver Channel Status register. The setting of the CHS bit in the Channel Status Data Buffer Control register determines whether the channel status decodes are from the A channel (CHS = 0) or B channel (CHS = 1). The PRO (professional) bit is extracted directly. Also, for consumer data, the COPY (copyright) bit is extracted, and the category code and L bits are decoded to determine SCMS status, indicated by the ORIG (original) bit. Finally, the AUDIO bit is extracted, and used to set an AUDIO indicator, as described in the Non-Audio Auto Detection section below. If 50/15 s pre-emphasis is detected, then this is reflected in the state of the EMPH pin. The encoded sample word length channel status bits are decoded according to AES3-1992 or IEC 60958. If the AES3 receiver is the data source for the SRC, then the SRC audio input data is truncated according to the channel status word length settings. Audio data routed to the serial audio output port is unaffected by the word length settings; all 24 bits are passed on as received. "Channel Status and User Data Buffer Management" on page 81 describes the overall handling of CS and U data.
7.1.5
User Data Handling
The incoming user data is buffered in a user-accessible buffer. Various automatic modes of re-transmitting received U data are provided. "Channel Status and User Data Buffer Management" on page 81 describes the overall handling of CS and U data. Received U data may also be output to the U pin, under the control of a control register bit. Depending on the data flow and clocking options selected, there may not be a clock available to qualify the U data output. Figure 19 illustrates the timing. If the incoming user data bits have been encoded as Q-channel subcode, the data is decoded and presented in 10 consecutive register locations. An interrupt may be enabled to indicate the decoding of a new Q-channel block, which may be read via the control port.
RCBL out VLRCK C, U Output
RCBL and C output are only available in hardware mode 5. RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames. VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CU timing. VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate. If no SRC is used, and the serial audio output port is in master mode, VLRCK = OLRCK. If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required. C, U transitions are aligned within 1% of VLRCK period to VLRCK edges
Figure 19. AES3 Receiver Timing for C & U Pin Output Data
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CS8420
7.1.6 Non-Audio Auto Detection
Since it is possible to convey non-audio data in an AES3 data stream, it is important to know whether the incoming AES3 data stream is digital audio or other data. This information is typically conveyed in channel status bit 1 (AUDIO), which is extracted automatically by the CS8420. However, certain non-audio sources, such as AC-3(R) or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8420 AES3 receiver can detect such non-audio data. This is accomplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F. When the sync code is detected, an internal AUTODETECT signal will be asserted. If no additional sync codes are detected within the next 4096 frames, AUTODETECT will be de-asserted until another sync code is detected. The AUDIO bit in the Receiver Channel Status register is the logical OR of AUTODETECT and the received channel status bit 1. If non-audio data is detected, the data is still processed exactly as if it were normal audio. It is up to the user to mute the outputs as required.
7.2
AES3 Transmitter
The AES3 transmitter encodes and transmits audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multiplexed together and bi-phase mark-encoded. The resulting bit stream is then driven directly, or through a transformer, to an output connector. The transmitter is usually clocked from the output side clock domain of the sample rate converter. This clock may be derived from the clock input pin OMCK, or from the incoming data. In data flows with no SRC, and where OMCK is asynchronous to the data source, an interrupt bit is provided that will go high every time a data sample is dropped or repeated. The channel status (C) and user channel (U) bits in the transmitted data stream are taken from storage areas within the CS8420. The user can manipulate the contents of the internal storage with a microcontroller. The CS8420 will also run in one of several automatic modes. "Channel Status and User Data Buffer Management" on page 81 provides detailed descriptions of each automatic mode, and describes methods for accessing the storage areas. The transmitted user data can optionally be input via the U pin, under the control of a control port register bit. Figure 20 shows the timing requirements for inputting U data via the U pin.
7.2.1
Transmitted Frame and Channel Status Boundary Timing
The TCBL pin may be an input or an output, and is used to control or indicate the start of transmitted channel status block boundaries. In some applications, it may be necessary to control the precise timing of the transmitted AES3 frame boundaries. This may be achieved in 3 ways: 1) With TCBL configured as an input, and TCBL transitions high for >3 OMCK clocks, it will cause a frame start, and a new channel status block start. 2) If the AES3 output comes from the AES3 input, while there is no SRC, setting TCBL as output will cause AES3 output frame boundaries to align with AES3 input frame boundaries. 3) If the AES3 output comes from the serial audio input port while the port is in Slave mode, and TCBL is set to output, then the start of the A channel sub-frame will be aligned with the leading edge of ILRCK.
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CS8420
7.2.2 TXN and TXP Drivers
The line drivers are low-skew, low-impedance, differential outputs capable of driving cables directly. Both drivers are set to ground during reset (RST = low), when no AES3 transmit clock is provided, and optionally under the control of a register bit. The CS8420 also allows immediate mute of the AES3 transmitter audio data via a control register bit. External components are used to terminate and isolate the external cable from the CS8420. These components are detailed in "External AES3/SPDIF/IEC60958 Transmitter and Receiver Components" on page 78.
7.3
Mono Mode Operation
Currently, the AES3 standard is being updated to include options for 96-kHz sample rate operation. One method is to double the frame rate of the current format. This results in a 96-kHz sample rate, stereo signal carried over a single twisted pair cable. An alternate method is where the 2 sub-frames in a 48-kHz frame rate AES3 signal are used to carry consecutive samples of a mono signal, resulting in a 96-kHz sample rate stream. This allows older equipment, whose AES3 transmitters and receivers are not rated for 96-kHz frame rate operation, to handle 96-kHz sample rate information. In this "mono mode", 2 AES3 cables are needed for stereo data transfer. The CS8420 offers mono mode operation, both for the AES3 receiver and for the AES3 transmitter. Figure 21 shows the operation of mono mode in comparison with normal stereo mode. The receiver and transmitter sections may be independently set to mono mode via the MMR and MMT control bits. The receiver mono mode effectively doubles Fsi compared to the input frame rate. The clock output on the RMCK pin tracks Fsi, and so is doubled in frequency compared to stereo mode. In mono mode, A and B sub-frames are routed to the SRC inputs as consecutive samples. When the transmitter is in mono mode, either A or B SRC consecutive outputs are routed alternately to A and B sub-frames in the AES3 output stream. Which channel status block is transmitted is also selectable. For the AES3 input to serial audio port output data flow, in receiver mono mode, then the receiver will run at a frame rate of Fsi/2, and the serial audio output port will run at Fsi. Identical data will appear in both left and right data fields on the SDOUT pin. For the serial audio input port to AES3 transmitter data flow, in transmitter mono mode, then the input port will run at Fso audio sample rate, while the AES3 transmitter frame rate will be at Fso/2. The data from either consecutive left, or right, positions will be selected for transmitting in A and B sub-frames.
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CS8420
Tth
TCBL In or Out VLRCK
Tsetup
VCU Input SDIN Input TXP(N)
Thold VCU[0] VCU[1] VCU[2] VCU[3] VCU[4]
Data[4]
Data[5]
Data[6]
Data[7]
Data[8]
Z
Data[0]
Y
Data[1]
X
Data[2]
Y
Data[3]
X
Data[4]
AES3 Transmitter in Stereo Mode TCBL In or Out VLRCK U Input SDIN Input TXP(N) Output Z Tth
Tsetup = > 7.5 % AES3 frame time Thold = 0 Tth > 3 OMCK if TCBL is Input
U[0]
U[2]
Data[4]
Data[5]
Data[6]
Data[7]
Data[8]
Data[0]*
Y
Data[2]*
X
Data[4]*
*Assume MMTLR = 0 TXP(N) Z Data[1]* Output *Assume MMTLR = 1
Y
Data[3]*
X
Data[5]*
AES3 Transmitter in Mono Mode
Tsetup = > 15 % AES3 frame time Thold = 0 Tth > 3 OMCK if TCBL is Input
VLRCK is a virtual word clock, which may not exist, and is used to illustrate CUV timing. VLRCK duty cycle is 50% In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate. If the serial audio input port is .in slave mode and TCBL is an output, the VLRCK=ILRCK if SILRPOL=0 and VLRCK = ILRCK if SILRPOL = 1. If the serial audio input port is in master mode and TCBL is an input, the VLRCK=ILRCK if SILRPOL=0 and VLRCK= ILRCK if SILRPOL = 1.
Figure 20. AES3 Transmitter Timing for C, U and V Pin Input Data
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CS8420
RECEIVER STEREO MODE
96kHz Fsi A B A B In SRC 96kHz Fso Out A B A
TRANSMITTER STEREO MODE
96kHz stereo 96kHz frame rate AES3 Receiver
96kHz stereo 96kHz frame rate
AES3 B Transmitter
PLL
256x96kHz
OMCK (256, 384, or 512x 96kHz)
RECEIVER MONO MODE
96kHz mono 48kHz frame rate AES3 Receiver 96kHz Fsi A B * A B In SRC 96kHz Fso Out MMTLR A + B
TRANSMITTER MONO MODE
96kHz mono 48kHz frame rate
A
AES3 B Transmitter
PLL (x2)
256x96kHz OMCK (256, 384, or 512x 96kHz)
* A & B sub-frames data are time-multiplexed into consecutive samples
+ Consecutive samples are alternately routed to A & B sub-fames
TRANSMITTER TIMING SRC Aout A1 B1 STEREO A2 B2 Frame A1 MONO A1 B1 A2 A2 B2
RECEIVER TIMING Frame Incoming AES3 SRC Ain SRC Bin MONO Ain & Bin SRC A1 B1 A2 B2 A1 B1 A2 A1 B1 B2 A2 B2
SRC Bout Outgoing AES3 Outgoing AES3 A selected Outgoing AES3 B selected
STEREO
Frame
B1
B2
Figure 21. Mono Mode Operation Compared to Normal Stereo Operation
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CS8420 8.
8.1
AES3 TRANSMITTER AND RECEIVER
Sample Rate Converter
The equation for the group delay through the sample rate converter, with the serial ports in Master mode is: ((input interface delay + 43) / Fsi) + ((43 + output interface delay 0.5) / Fso) The unit of delay depends on the frame rate (sample rate) Fs. The AES receiver has a interface delay of 2 frames. The AES transmitter, the serial input port, and the serial output port each have an interface delay of 1 frame. The 0.5 frame delay in the second half of the equation is due to the start-up uncertainty of the logic within the part. When using multiple parts together, it is possible to start the parts simultaneously in a fashion that minimizes the relative group delay between the parts. When multiple parts are started together in the proper way, the variation in signal delay through the parts is 1.5 s. To start the parts simultaneously, set up each one so that the PLL will lock, with the active input port driving both output ports. Then simultaneously enable the RUN bits in all of the parts. TCBL on one of the CS8420 parts should be set as an output, while the remaining TCBL pins should be set as inputs. This synchronizes the AES transmitter on all of the parts. Depending upon software considerations, it may be advantageous to configure the registers so that an interrupt is generated on the INT pin when lock occurs. The control logic should either poll the unlock bits until all PLL's are locked or wait for the interrupts to indicate that all are locked, depending on which approach you've chosen. When all of the PLL's are locked, the CS8420's should be advanced to the next state together. Drive all the serial control ports together with the same clock and data. Change the configuration in register 03h according to Table 1 or Table 2. Register (HEX) 01 03 04 11 Initial Value (HEX) 01 or 00 95 41 10 Value After Advancing to the Running State, After the PLL's are Locked (HEX) 01 or 00 81 41 10
Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN
Register (HEX) 01 03 04 11
Initial Value (HEX) 01 or 00 8A 40 10
Value After Advancing to the Running State, After the PLL's are Locked (HEX) 01 or 00 80 40 10
Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK
28
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8.2 Non-SRC Delay
The unit of delay depends on the frame rate (sample rate) Fs. The AES receiver has a interface delay of two frames. The AES transmitter, the serial input port, and the serial output port each have an interface delay of 1 frame. The 0.5 frame delay in the second half of the equation is due to the startup uncertainty of the logic within the part. 1. All inputs are slaves and all outputs are masters, both with respect to the outside world. 2. The inputs and outputs are synchronous to one another. Path RX to TX Serial Input to TX RX to Serial Output Serial Input to Serial Output
Table 3. Non-SRC Delay
Delay (in units of a frame) 3 1/128 2 1/128 3 1/128 2 1/128
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CS8420 9. CONTROL PORT DESCRIPTION AND TIMING
The control port is used to access the registers, allowing the CS8420 to be configured for the desired operational modes and formats. In addition, Channel Status and User data may be read and written via the control port. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has two modes: SPI and IC, with the CS8420 acting as a slave device. SPI mode is selected if there is a high-to-low transition on the AD0/CS pin after the RST pin has been brought high. IC mode is selected by connecting the AD0/CS pin to VD+ or DGND, thereby permanently selecting the desired AD0 bit address state.
9.1
SPI Mode
In SPI mode, CS is the CS8420 chip select signal. CCLK is the control port bit clock (input into the CS8420 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. Figure 22 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address and must be 0010000b. The eighth bit is a read/write indicator (R/W), which should be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if desired.
CS
CCLK C H IP ADDRESS C D IN 0010000 R/W C H IP ADDRESS LSB b y te n MSB LSB MSB LSB
MAP MSB
DATA
0010000
R/W
b y te 1 High Impedance CDOUT
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 22. Control Port Timing in SPI Mode
There is a MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, then the MAP will stay constant for successive read or writes. If INCR is set to a 1, then the MAP will autoincrement after each byte is read or written, allowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the highimpedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear consecutively.
30
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9.2 IC Mode
In IC mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 23. There is no CS pin. Each individual CS8420 is given a unique address. Pins AD[1:0] form the two least significant bits of the chip address and should be connected to VD+ or DGND as desired. The EMPH pin is used to set the AD2 bit, by connecting a resistor from the EMPH pin to VD+ or to DGND. The state of the pin is sensed while the CS8420 is being reset. The upper four bits of the 7-bit address field are fixed at 0010b. To communicate with a CS8420, the chip address field, which is the first byte sent to the CS8420, should match 0010b followed by the settings of the EMPH, AD1, and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS8420 after each input byte is read and is input to the CS8420 from the microcontroller after each transmitted byte.
Note 1 SDA 0010 AD2-0 R/W ACK
Note 2 DATA7-0 ACK DATA7-0
Note 3 ACK
SCL Start Notes: 1. AD2 is derived from a resistor attached to the EMPH pin AD1, and AD0 are determined by the state of the corresponding pins. Stop
2. If operation is a write, this byte contains the Memory Address Pointer, MAP. 3. If operation is a read, the last bit of the read should be NACK (high).
Figure 23. Control Port Timing in IC Mode
9.3
Interrupts
The CS8420 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin on the host microcontroller. The INT pin may be set to be active-low, active-high, or active-low with no active pull-up transistor. This last mode is used for active-low, wired-OR hook-ups, with multiple peripherals connected to the microcontroller interrupt input pin. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each source may be masked via mask registers. In addition, each source may be set to rising-edge, falling-edge, or levelsensitive. Combined with the option of level-sensitive or edge-sensitive modes within the microcontroller, many different set-ups are possible, depending on the needs of the equipment designer.
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CS8420 10. CONTROL PORT REGISTER BIT DEFINITIONS
10.1 Memory Address Pointer (MAP)
6 MAP6 5 MAP5 4 MAP4 3 MAP3 2 MAP2 1 MAP1 0 MAP0
7 INCR
This register defaults to 01 INCR Auto-Increment Address Control Bit 0Auto-increment address off 1Auto-increment address on Register address and function list 0Reserved 1Misc. Control 1 2Misc. Control 2 3Data Flow Control 4Clock Source Control 5Serial Audio Input Port Data Format 6Serial Audio Output Port Data Format 7Interrupt Register 1 Status 8Interrupt Register 2 Status 9Interrupt Register 1 Mask 10 Interrupt Register1 Mode (MSB) 11 Interrupt Register 1 Mode (LSB) 12 Interrupt Register 2 Mask 13 Interrupt Register 2 Mode (MSB) 14 Interrupt Register 2 Mode (LSB) 15 Receiver Channel Status Bits 16 Receiver Error Status 17 Receiver Error Mask 18 Channel Status Data Buffer Control 19 User Data Buffer Control 20 to 29 - Q-channel Subcode Bytes 0 to 9 30 Sample Rate Ratio 31 Reserved 32 to 55 - C-bit or U-bit Data Buffer 56 to 126 - Reserved 127 Chip ID and version register
MAP6-MAP0
Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8420.
32
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Addr (HEX) 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14-1D 1E 20-37 7F
Function Control 1 Control 2 Data Flow Control Clock Source Control Serial Input Format Serial Output Format Interrupt 1 Status Interrupt 2 Status Interrupt 1 Mask Interrupt 1 Mode (MSB) Interrupt 1 Mode (LSB) Interrupt 2 Mask Interrupt 2 Mode (MSB) Interrupt 2 Mode (LSB) Receiver CS Data Receiver Errors Receiver Error Mask CS Data Buffer Control U Data Buffer Control Q Sub-Code Data Sample Rate Ratio C or U Data Buffer ID and Version
7
SWCLK TRUNC AMLL 0 SIMS SOMS TSLIP 0 TSLIP1 TSLIP0 0 0 0 AUX3 0 0 0 0 SRR7 ID3
6
VSET HOLD1 TXOFF RUN SISF SOSF OSLIP 0 OSLIP1 OSLIP0 0 0 0 AUX2 QCRC QCRCM 0 0 SRR6 ID2
5
MUTESAO HOLD0 AESBP CLK1 SIRES1 SORES1 SRE VFIFO SREM SRE1 SRE0 VFIFOM VFIFO1 VFIFO0 AUX1 CCRC CCRCM BSEL 0 SRR5 ID1
4
MUTEAES RMCKF TXD1 CLK0 SIRES0 SORES0 OVRGL REUNLOCK OVRGLM OVRGL1 OVRGL0 REUNLOCKM REUNLOCK1 REUNLOCK0 AUX0 UNLOCK UNLOCKM CBMR UD SRR4 ID0
3
DITH MMR TXD0 OUTC SIJUST SOJUST OVRGR DETU OVRGR1 OVRGR0 DETUM DETU1 DETU0 PRO V VM DETCI UBM1 SRR3 VER3
2
INT1 MMT SPD1 INC SIDEL SODEL DETC EFTU DETC1 DETC0 EFTUM EFTU1 EFTU0 AUDIO CONF CONFM EFTCI UBM0 SRR2 VER2
1
INT0 MMTCS SPD0 RXD1 SISPOL EFTC QCH EFTCM EFTC1 EFTC0 QCHM QCH1 QCH0 COPY BIP BIPM CAM DETUI SRR1 VER1
0
TCBLD MMTLR SRCD RXD0 SILRPOL RERR UOVW RERRM RERR1 RERR0 UOVWM UOVW1 UOVW0 ORIG PAR PARM CHS EFTUI SRR0 VER0
SOSPOL SOLRPOL
TSLIPM OSLIPM
OVRGRM DETCM
Table 4. Summary of all Bits in the Control Register Map
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CS8420
10.2 Miscellaneous Control 1 (01h)
6 VSET 5 MUTESAO 4 MUTEAES 3 DITH 2 INT1 1 INT0 0 TCBLD 7 SWCLK
SWCLK
Causes OMCK to be output through the RMCK pin when the PLL is unlocked 0 - RMCK is driven by the PLL VCO (default) 1 - OMCK is switched to output through the RMCK pin when the PLL is unlocked. Circuitry driven by the PLL is driven by OMCK. Transmitted V bit level 0 - Transmit a 0 for the V bit, indicating that the data is valid, and is normally linear PCM audio (default) 1 - Transmit a 1 for the V bit, indicating that the data is invalid or is not linear PCM audio data Mute control for the serial audio output port 0 - Normal output (default) 1 - Mute the serial audio output port Mute control for the AES3 transmitter output 0 - Normal output (default) 1 - Mute the AES3 transmitter output Dither Control 0 - Triangular PDF dither applied to output data. The level of the dither is automatically adjusted to be appropriate for the output word length selected by the SORES bits (default) 1 - No dither applied to output data. Interrupt (INT) output pin control 00 - Active high, high output indicates an interrupt condition has occurred (default) 01 - Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. This setting requires an external pull up resistor on the INT pin. 11 - Reserved Transmit Channel Status Block pin (TCBL) direction specifier 0 - TCBL is an input (default) 1 - TCBL is an output
VSET
MUTESAO
MUTEAES
DITH
INT[1:0]
TCBLD
34
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10.3 Miscellaneous Control 2 (02h)
6 HOLD1 5 HOLD0 4 RMCKF 3 MMR 2 MMT 1 MMTCS 0 MMTLR 7 TRUNC
TRUNC
Determines whether the word length is set according to the incoming Channel Status data 0 - Data to the SRC is not truncated (default) 1 - Data to the SRC is set according to the AUX field in the incoming data stream The HOLD bits determine how the received audio sample is affected when a receiver error occurs. 00 - Hold the last valid audio sample (default) 01 - Replace the current audio sample with 00 (mute) 10 - Do not change the received audio sample 11 - Reserved Select recovered master clock output pin frequency. 0 - RMCK is equal to 256 * Fsi (default) 1 - RMCK is equal to 128 * Fsi Select AES3 receiver mono or stereo operation 0 - Interpret A and B subframes as two independent channels (normal stereo operation, default) 1 - Interpret A and B subframes as consecutive samples of one channel of data.This data is duplicated to both left and right parallel outputs of the AES receiver block. The input sample rate (Fsi) is doubled compared to MMR=0 Select AES3 transmitter mono or stereo operation 0 - Outputs left channel input into A subframe and right channel input into B subframe (normal stereo operation, default). 1 - Output either left or right channel inputs into consecutive subframe outputs (mono mode, left or right is determined by MMTLR bit) Select A or B channel status data to transmit in mono mode 0 - Use channel A CS data for the A sub-frame slot and use channel B CS data for the B subframe slot (default) 1 - Use the same CS data for both the A and B sub-frame output slots. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data. Channel Selection for AES Transmitter mono mode 0 - Use left channel input data for consecutive sub-frame outputs (default) 1 - Use right channel input data for consecutive sub-frame outputs
HOLD[1:0]
RMCKF
MMR
MMT
MMTCS
MMTLR
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CS8420
10.4 Data Flow Control (03h)
6 TXOFF 5 AESBP 4 TXD1 3 TXD0 2 SPD1 1 SPD0 0 SRCD 7 AMLL
The Data Flow Control register configures the flow of audio data to/from the following blocks: Serial Audio Input Port, Serial Audio Output Port, AES3 receiver, AES3 transmitter, and Sample Rate Converter. In conjunction with the Clock Source Control register, multiple Receiver/Transmitter/Transceiver modes may be selected. The output data should be muted prior to changing bits in this register to avoid transients. AMLL Auto Mutes the SRC data sink when Receiver lock is lost, zero data is transmitted. The SRC data sink may be either, or both, the Transmitter and the Serial Audio Output Port. 0 - Disables Auto Mute on loss of lock (default) 1 - Enables Auto Mute on loss of lock AES3 Transmitter Output Driver Control 0 - AES3 transmitter output pin drivers normal operation (default) 1 - AES3 transmitter output pin drivers drive to 0 V. AES3 bypass mode selection 0 - normal operation 1 - Connect the AES3 transmitter driver input directly to the RXP pin, which become a normal TTL threshold digital input. AES3 Transmitter Data Source 00 - SRC output (default) 01 - Serial audio input port 10 - AES3 receiver 11 - Reserved Serial Audio Output Port Data Source 00 - SRC output (default) 01 - Serial Audio Input Port 10 - AES3 receiver 11 - Reserved Input Data Source for SRC 0 - Serial Audio Input Port (default) 1 - AES3 Receiver
TXOFF
AESBP
TXD[1:0]
SPD[1:0]
SRCD
36
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10.5
7 0
Clock Source Control (04h)
6 RUN 5 CLK1 4 CLK0 3 OUTC 2 INC 1 RXD1 0 RXD0
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, various Receiver/Transmitter/Transceiver modes may be selected. RUN The RUN bit controls the internal clocks, allowing the CS8420 to be placed in a "powered down", low current consumption, state. 0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port is operational, allowing registers to be read or changed. Reading and writing the U and C data buffers is not possible. Power consumption is low (default). 1 - Normal part operation. This bit must be written to the 1 state to allow the CS8420 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If these bits are changed during normal operation, then always stop the CS8420 first (RUN = 0), then write the new value, then start the CS8420 (RUN = 1). 00 - OMCK frequency is 256*Fso(default) 01 - OMCK frequency is 384*Fso 10 - OMCK frequency is 512*Fso 11 - reserved Output Time Base 0 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0, (default) 1 - Recovered Input Clock Input Time Base Clock Source 0 - Recovered Input Clock (default) 1 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0) Recovered Input Clock Source 00 - 256*Fsi, where Fsi is derived from the ILRCK pin (only possible when the serial audio input port is in Slave mode, default) 01 - 256*Fsi, where Fsi is derived from the AES3 input frame rate 10 - Bypass the PLL and apply an external 256*Fsi clock via the RMCK pin. The AES3 receiver is held in synchronous reset. This setting is useful to prevent UNLOCK interrupts when using an external RMCK and inputting data via the serial audio input port. 11 - Reserved
CLK[1:0]
OUTC
INC
RXD[1:0]
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CS8420
10.6 Serial Audio Input Port Data Format (05h)
6 SISF 5 SIRES1 4 SIRES0 3 SIJUST 2 SIDEL 1 SISPOL 0 SILRPOL 7 SIMS
SIMS
Master/Slave Mode Selector 0 - Serial audio input port is in Slave mode (default) 1 - Serial audio input port is in Master mode ISCLK frequency (for Master mode) 0 - 64*Fsi (default) 1 - 128*Fsi Resolution of the input data, for right-justified formats 00 - 24 bit resolution (default) 01 - 20 bit resolution 10 - 16 bit resolution 11 - Reserved Justification of SDIN data relative to ILRCK 0 - Left-Justified (default) 1 - Right-Justified Delay of SDIN data relative to ILRCK, for left-justified data formats 0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (default) 1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge ISCLK clock polarity 0 - SDIN sampled on rising edges of ISCLK (default) 1 - SDIN sampled on falling edges of ISCLK ILRCK clock polarity 0 - SDIN data is for the left channel when ILRCK is high (default) 1 - SDIN data is for the right channel when ILRCK is high
SISF
SIRES[1:0]
SIJUST
SIDEL
SISPOL
SILRPOL
38
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CS8420
10.7 Serial Audio Output Port Data Format (06h)
6 SOSF 5 SORES1 4 SORES0 3 SOJUST 2 SODEL 1 SOSPOL 0 SOLRPOL 7 SOMS
SOMS
Master/Slave Mode Selector 0 - Serial audio output port is in Slave mode (default) 1 - Serial audio output port is in Master mode OSCLK frequency (for Master mode) 0 - 64*Fso (default) 1 - 128*Fso Resolution of the output data on SDOUT and AES3 output when the sample rate converter is set as the source 00 - 24 bit resolution (default) 01 - 20 bit resolution 10 - 16 bit resolution 11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and V bits, the time slot normally occupied by the P bit is used to indicate the location of the block start, SDOUT pin only, serial audio output port clock must be derived from the AES3 receiver recovered clock) Justification of SDOUT data relative to OLRCK 0 - Left-Justified (default) 1 - Right-Justified (Master mode only) Delay of SDOUT data relative to OLRCK, for left-justified data formats 0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge (default) 1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge OSCLK clock polarity 0 - SDOUT transitions occur on falling edges of OSCLK (default) 1 - SDOUT transitions occur on rising edges of OSCLK OLRCK clock polarity 0 - SDOUT data is for the left channel when OLRCK is high (default) 1 - SDOUT data is for the right channel when OLRCK is high
SOSF
SORES[1:0]
SOJUST
SODEL
SOSPOL
SOLRPOL
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CS8420
10.8 Interrupt 1 Register Status (07h) (Read Only)
6 OSLIP 5 SRE 4 OVRGL 3 OVRGR 2 DETC 1 EFTC 0 RERR 7 TSLIP
For all bits in this register, a "1" means the associated interrupt condition has occurred at least once since the register was last read. A"0" means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be "0" in this register. This register defaults to 00. TSLIP AES3 transmitter source data slip interrupt. In data flows with no SRC, and where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time a data sample is dropped or repeated. Also, when TCBL is an input, and when the SRC is not in use, this bit will go high on receipt of a new TCBL signal. Serial audio output port data slip interrupt. When the serial audio output port is in Slave mode, and OLRCK is asynchronous to the port data source, this bit will go high every time a data sample is dropped or repeated. Also, when the SRC is used, and the SRC output goes to the output serial port configured in Slave mode, this bit will indicate if the ratio of OMCK frequency to OLRCK frequency does not match what is set in the CLK1 and CLK0 bits. Sample rate range exceeded indicator. Occurs if Fsi/Fso or Fso/Fsi exceeds 3. Over-range indicator for left (A) channel SRC output. Occurs on internal over-range for left channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale. Over-range indicator for right (B) channel SRC output. Occurs on internal over-range for right channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale D to E C-buffer transfer interrupt. The source for this bit is true during the D to E buffer transfer in the C bit buffer management process. E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer in the C bit buffer management process. A receiver error has occurred. The Receiver Error register may be read to determine the nature of the error which caused the interrupt.
OSLIP
SRE OVRGL OVRGR DETC EFTC RERR
40
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CS8420
10.9
7
0
Interrupt Register 2 Status (08h) (Read Only)
6
0
5
VFIFO
4
REUNLOCK
3
DETU
2
EFTU
1
QCH
0
UOVW
For all bits in this register, a "1" means the associated interrupt condition has occurred at least once since the register was last read. A"0" means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be "0" in this register. This register defaults to 00. VFIFO REUNLOCK DETU EFTU QCH UOVW Varispeed FIFO overflow indicator. Occurs if the data buffer in the SRC overflows. This will occur if the input sample rate slows too fast. Sample rate converter unlock indicator. This interrupt occurs if the SRC is still tracking a changing input or output sample rate. D to E U-buffer transfer interrupt. The source of this bit is true during the D to E buffer transfer in the U bit buffer management process (block mode only). E to F U-buffer transfer interrupt. The source of this bit is true during the E to F buffer transfer in the U bit buffer management process (block mode only). A new block of Q-subcode data is available for reading. The data must be completely read within 588 AES3 frames after the interrupt occurs to avoid corruption of the data by the next block. U-bit FIFO Overwrite. This interrupt occurs on an overwrite in the U-bit FIFO.
10.10 Interrupt 1 Register Mask (09h)
7 TSLIPM 6 OSLIPM 5 SREM 4 OVRGLM 3 OVRGRM 2 DETCM 1 EFTCM 0 RERRM
The bits of this register serve as a mask for the Interrupt 1 Register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in Interrupt Register 1. This register defaults to 00.
10.11 Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh)
7 TSLIP1 TSLIP0 6 OSLIP1 OSLIP0 5 SRE1 SRE0 4 OVRGL1 OVRGL0 3 OVRGR1 OVRGR0 2 DETC1 DETC0 1 EFTC1 EFTC0 0 RERR1 RERR0
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. This code determines whether the INT pin is set active on the arrival of the interrupt condition, on the removal of the interrupt condition, or on the continuing occurrence of the interrupt condition. These registers default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved
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CS8420
10.12 Interrupt 2 Register Mask (0Ch)
7 0 6 0 5 VFIFOM 4 REUNLOCKM 3 DETUM 2 EFTUM 1 QCHM 0 UOVWM
The bits of this register serve as a mask for the Interrupt 2 Register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in Interrupt Register 2. This register defaults to 00.
10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh)
7 0 0 6 0 0 5 VFIFO1 VFIFO0 4 REUNLOCK1 REUNLOCK0 3 DETU1 DETU0 2 EFTU1 EFTU0 1 QCH1 QCH0 0 UOVW1 UOVW0
The two Interrupt mode registers form a 2-bit code for each Interrupt 2 register function. This code determines whether the INT pin is set active on the arrival of the interrupt condition, on the removal of the interrupt condition, or on the continuing occurrence of the interrupt condition. These registers default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved
42
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CS8420
10.14 Receiver Channel Status (0Fh) (Read Only)
7 AUX3 6 AUX2 5 AUX1 4 AUX0 3 PRO 2 AUDIO 1 COPY 0 ORIG
The bits in this register can be associated with either channel A or B of the received data. The desired channel is selected with the CHS bit of the Channel Status Data Buffer Control Register. AUX[3:0] The AUX3-0 bits indicate the width of the incoming auxiliary data field, as indicated by the incoming channel status bits, decoded according to IEC60958 and AES3. 0000 - Auxiliary data is not present 0001 - Auxiliary data is 1 bit long 0010 - Auxiliary data is 2 bits long 0011 - Auxiliary data is 3 bits long 0100 - Auxiliary data is 4 bits long 0101 - Auxiliary data is 5 bits long 0110 - Auxiliary data is 6 bits long 0111 - Auxiliary data is 7 bits long 1000 - Auxiliary data is 8 bits long 1001 - 1111 Reserved Channel status block format indicator 0 - Received channel status block is in consumer format 1 - Received channel status block is in professional format Audio indicator 0 - Received data is linearly coded PCM audio 1 - Received data is not linearly coded PCM audio SCMS copyright indicator 0 - Copyright asserted 1 - Copyright not asserted SCMS generation indicator. This is decoded from the category code and the L bit. 0 - Received data is 1st generation or higher 1 - Received data is original COPY and ORIG will both be set to 1 if the incoming data is flagged as professional or if the receiver is not in use.
PRO
AUDIO
COPY
ORIG
Note:
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CS8420
10.15 Receiver Error (10h) (Read Only)
7 0 6 QCRC 5 CCRC 4 UNLOCK 3 V 2 CONF 1 BIP 0 PAR
This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of the error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the error source is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register. This register defaults to 00. QCRC Q-subcode data CRC error has occurred. Updated on Q-subcode block boundaries. 0 - No error 1 - Error Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries. This bit is valid in Professional mode only. 0 - No error 1 - Error PLL lock status bit. Updated on CS block boundaries. 0 - PLL locked 1 - PLL out of lock Received AES3 Validity bit status. Updated on sub-frame boundaries. 0 - Data is valid and is normally linear coded PCM audio 1 - Data is invalid, or may be valid compressed audio Confidence bit. Updated on sub-frame boundaries. 0 - No error 1 - Confidence error. This indicates that the received data eye opening is less than half a bit period, indicating a poor link that is not meeting specifications. Bi-phase error bit. Updated on sub-frame boundaries. 0 - No error 1 - Bi-phase error. This indicates an error in the received bi-phase coding. Parity bit. Updated on sub-frame boundaries. 0 - No error 1 - Parity error
CCRC
UNLOCK
V
CONF
BIP
PAR
44
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CS8420
10.16 Receiver Error Mask (11h)
7 0 6 QCRCM 5 CCRCM 4 UNLOCKM 3 VM 2 CONFM 1 BIPM 0 PARM
The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will appear in the receiver error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the current audio sample according to the status of the HOLD bit. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not appear in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio sample even when unmasked. This register defaults to 00.
10.17 Channel Status Data Buffer Control (12h)
7 0 6 0 5 BSEL 4 CBMR 3 DETCI 2 EFTCI 1 CAM 0 CHS
BSEL
Selects the data buffer register addresses to contain User data or Channel Status data 0 - Data buffer address space contains Channel Status data (default) 1 - Data buffer address space contains User data Control for the first 5 bytes of channel status "E" buffer 0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data (default) 1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data D to E C-data buffer transfer inhibit bit. 0 - Allow C-data D to E buffer transfers (default) 1 - Inhibit C-data D to E buffer transfers E to F C-data buffer transfer inhibit bit. 0 - Allow C-data E to F buffer transfers (default) 1 - Inhibit C-data E to F buffer transfers C-data buffer control port access mode bit 0 - One byte mode 1 - Two byte mode Channel select bit 0 - Channel A information is displayed at the EMPH pin and in the receiver channel status register. Channel A information is output during control port reads when CAM is set to 0 (One Byte Mode) 1 - Channel B information is displayed at the EMPH pin and in the receiver channel status register. Channel B information is output during control port reads when CAM is set to 0 (One Byte Mode)
CBMR
DETCI
EFTCI
CAM
CHS
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CS8420
10.18 User Data Buffer Control (13h)
7 0 6 0 5 0 4 UD 3 UBM1 2 UBM0 1 DETUI 0 EFTUI
UD
User data pin (U) direction specifier 0 - The U pin is an input. The U data is latched in on both rising and falling edges of OLRCK. This setting also chooses the U pin as the source for transmitted U data (default). 1 - The U pin is an output. The received U data is clocked out on both rising and falling edges of ILRCK. This setting also chooses the U data buffer as the source of transmitted U data. Sets the operating mode of the AES3 U bit manager 00 - Transmit all zeros mode (default) 01 - Block mode 10 - Reserved 11 - IEC consumer mode B D to E U-data buffer transfer inhibit bit (valid in block mode only). 0 - Allow U-data D to E buffer transfers (default) 1 - Inhibit U-data D to E buffer transfers E to F U-data buffer transfer inhibit bit (valid in block mode only). 0 - Allow U-data E to F buffer transfers (default) 1 - Inhibit U-data E to F buffer transfer
UBM[1:0]
DETUI
EFTUI
Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only)
The following 10 registers contain the decoded Q-channel subcode data
7 6 5 4 3 2 1 0 CONTROL CONTROL CONTROL CONTROL ADDRESS ADDRESS ADDRESS ADDRESS TRACK TRACK TRACK TRACK TRACK TRACK TRACK TRACK INDEX INDEX INDEX INDEX INDEX INDEX INDEX INDEX MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE SECOND SECOND SECOND SECOND SECOND SECOND SECOND SECOND FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME
Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 14h is Q[0] while bit 0 of address 14h is Q[7]. Similarly bit 0 of address 1Dh corresponds to Q[79].
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10.19 Sample Rate Ratio (1Eh) (Read Only)
7 SRR7 6 SRR6 5 SRR5 4 SRR4 3 SRR3 2 SRR2 1 SRR1 0 SRR0
The Sample Rate Ratio is Fso divided by Fsi. This value is represented as an integer and a fractional part. The value is meaningful only after the both the PLL and SRC have reached lock, and the SRC output is being used SRR[7:6 SRR[5:0] The integer part of the sample rate ratio The fractional part of the sample rate ratio
10.20 C-Bit or U-Bit Data Buffer (20h - 37h)
Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is accessible via these register addresses.
10.21 CS8420 I.D. and Version Register (7Fh) (Read Only)
7 ID3 6 ID2 5 ID1 4 ID0 3 VER3 2 VER2 1 VER1 ID3 VER0
ID[3:0] VER[3:0]
ID code for the CS8420. Permanently set to 0001 CS8420 Revision Level: Revision B is coded as 0001 Revision C is coded as 0011 Revision D is coded as 0100
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CS8420 11. SYSTEM AND APPLICATIONS ISSUES
11.1 Reset, Power Down and Start-up Options
When RST is low, the CS8420 enters a low-power mode. All internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port becomes operational, and the desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then cause the part to leave the low-power state and begin operation. After the PLL and the SRC have settled, the AES3 and serial audio outputs will be enabled. Some options within the CS8420 are controlled by a start-up mechanism. During the reset state, some of the output pins are reconfigured internally to be inputs. Immediately upon exiting the reset state, the level of these pins is sensed. The pins are then switched to be outputs. This mechanism allows output pins to be used to set alternative modes in the CS8420 by connecting a 47 k resistor between the pin and either VD+ (High) or DGND (Low). For each mode, every start-up option select pin MUST have an external pull-up or pull-down resistor. In software mode, the only start-up option pin is EMPH, which is used to set a chip address bit for the control port in IC mode. Hardware modes use many start-up options, which are detailed in the hardware definition section at the end of this data sheet.
11.2
Transmitter Startup
When the CS8420 is taken out of power-down and the AES3 receiver is configured to be in-circuit, the part uses the clock recovered from the AES3 input stream to advance its internal state machine to run. This can be a problem if no valid AES3 stream is present at the RXP/RXN pins and data input through the serial audio port needs to be output through the AES3 transmitter. To complete initialization and begin operation when the AES3 receiver is in-circuit and no valid AES3 input stream is presented to the RXP/RXN pins, the user must execute the following sequence: 1. Place the CS8420 in power-down (RUN = 0). 2. Set the serial audio input and output ports to Slave mode (SIMS = 0, SOMS = 0). 3. Set the input and output time base to the OMCK input pin (OUTC = 0, INC = 1). 4. Configure the SRC to receive its input from the serial audio input port (SRCD = 0). 5. Configure the serial audio output port to receive its input from the serial audio input port (SPD[1:0] = 01). 6. Configure the AES3 transmitter to receive its input from the serial audio input port (TXD[1:0] = 01). 7. Set the RUN bit (RUN = 1). After completing steps 1-7, the transmitter will function properly, and the data flow can be altered for the application without powering down.
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11.3 SRC Invalid State
Occasionally the CS8420 SRC will enter an invalid state. This can happen after the RUN bit has been set when an AES3 stream is first plugged into the part or when a source device interrupts the SRC input stream. When this happens, two symptoms may be noticeable: notches occurring in the frequency response and spurious tones being generated in response to some input frequencies. To avoid this problem in Software mode, use the microcontroller to monitor the UNLOCK bit in control register 10h. When the part achieves lock, clear the RUN bit in register 4 and then set it again. This will reset all internal state machines. Alternately, the user may use the following sequence: 1. Power on CS8420. 2. Write the following register sequence: Register 04h 03h 04h 3. Wait for PLL to lock. 4. Wait 250ms for SRC to lock. 5. Write the following register sequence: Register 03h 04h 6. If PLL goes out of lock, start at step 2 and repeat. When synchronizing multiple CS8420s, wait for all PLLs to lock before continuing to the next step. These actions clear the invalid state if it has occurred. In Hardware mode, monitor the RERR pin for receiver lock status. When the part achieves lock, set the RST pin low for at least 200 s and then set it high again. This action clears the invalid state if it has occurred. When polling the RERR pin again, the user must account for the fact that the RERR pin will be high during reset and remain high until the PLL has reachieved lock. In either Software or Hardware mode, when clearing the invalid state, it is advisable to mute any devices connected to the output of the CS8420. Value 81h 41h Value 09h 95h 49h
11.4
C/U Buffer Data Corruption
Occasionally the C/U buffer data may be corrupted. This can happen after the RUN bit has been set and data has been written to the C/U buffer (20h-37h). If no further data is written to the C buffer after the initial write and the receiver input is interrupted multiple times, the contents of the buffer may be reset to all zeros. The buffer will not be corrupted if the buffer data is being updated, only when the data is static and the receiver input has been interrupted multiple times. To avoid this problem in Software mode when the C/U buffer contents should remain static, use the microcontroller to monitor the UNLOCK bit in control register 10h or the RERR pin. If the part indicates the PLL has lost lock, rewrite the C/U buffer data. Repeat this action every time the PLL goes out of lock. In Hardware mode, this limitation does not exist as the serial C/U data is being fed directly to the transmitter.
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11.5 Block-Mode U-Data D-to-E Buffer Transfers
When Fsi Fso, Block-Mode U-data transfers from the D buffer to the E buffer are not synchronous to the input clock domain. D-to-E buffer transfers can always be detected by the activation of the DETU bit (bit 3 in register 08h) when Fsi Fso or Fsi = Fso. IEC Consumer B mode, serial U-data output, and the Qchannel subcode bytes (registers 14h - 1Dh) are unaffected by the input/output sample rate relationship.
11.6
ID Code and Revision Code
The CS8420 has a register that contains a 4-bit code to indicate that the addressed device is a CS8420. This is useful when other CS84xx family members are resident in the same system, allowing common software modules. The CS8420 4-bit revision code is also available. This allows the software driver for the CS8420 to identify which revision of the device is in a particular system, and modify its behavior accordingly. To allow for future revisions, it is strongly recommend that the revision code is read into a variable area within the microcontroller, and used wherever appropriate as revision details become known.
11.7
Power Supply, Grounding, and PCB layout
For most applications, the CS8420 can be operated from a single +5V supply, following normal supply decoupling practice (see Figure 5. "Recommended Connection Diagram for Software Mode" on page 12). For applications where the recovered input clock, output on the RMCK pin, is required to be low-jitter, then use a separate, quiet, analog +5V supply for VA+, decoupled to AGND. In addition, a separate region of analog ground plane around the FILT, AGND, VA+, RXP and RXN pins is recommended. The VD+ supply should be well-decoupled with a 0.1 F capacitor to DGND to minimize AES3 transmitter induced transients. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Make sure decoupling capacitors are mounted on the same side of the board as the CS8420, to minimize via inductance effects. All decoupling capacitors should be as close to the CS8420 as possible.
11.8
Synchronization of Multiple CS8420s
The serial audio output ports of multiple CS8420s can be synchronized by sharing the same master clock, OSCLK, OLRCK, and RST line and ensuring that all devices leave the reset state on the same master clock falling edge. Either all the ports need to be in Slave mode, or one can be set as a master. The AES3 transmitters may be synchronized by sharing the same master clock, TCBL, and RST signals, and ensuring all devices leave the reset state on the same master clock falling edge. The TCBL pin is used to synchronize multiple CS8420 AES3 transmitters at the channel status block boundaries. One CS8420 must have its TCBL set to master; the others must be set to slave TCBL. Alternatively, TCBL can be derived from some external logic, in which case all the CS8420 devices should be set to slave TCBL.
11.9
Extended Range Sample Rate Conversion
For handling sampling rate conversion ratios greater than 3:1 or less than 1:3, the user can use a cascade of two devices. The product of the conversion ratio of the two devices should equal the target conversion ratio.
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CS8420 12. SOFTWARE MODE - PIN DESCRIPTION
The above diagram and the following pin descriptions apply to Software mode. In Hardware mode, some pins change their function as described in subsequent sections of this data sheet. Fixed function pins are marked with a *, and will be described once in this section. Pins marked with a + are used upon reset to select various start-up options, and require a pull-up or pull-down resistor.
Power Supply Connections:
VD+ - Positive Digital Power * Positive supply for the digital section. Nominally +5.0 V. VA+ - Positive Analog Power * Positive supply for the analog section. Nominally +5.0 V. This supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock. DGND - Digital Ground * Ground for the digital section. DGND should be connected to the same ground as AGND. AGND - Analog Ground * Ground for the analog section. AGND should be connected to the same ground as DGND.
Clock-Related Pins:
OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x, 384x, or 512x the output sample rate (Fso). RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 128x or 256x the input sample rate (Fsi).
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FILT - PLL Loop Filter * An RC network should be connected between this pin and ground. Recommended schematic and component values are given in "PLL Filter" on page 87.
Overall Device Control:
H/S - Hardware or Software Control Mode Select * The H/S pin determines the method of controlling the operation of the CS8420, and the method of accessing CS and U data. In Software mode, device control and CS and U data access is primarily via the control port, using a microcontroller. In Hardware mode, alternate modes and access to CS and U data is provided by pins. This pin should be permanently tied to VD+ or DGND. RST - Reset Input * When RST is low, the CS8420 enters a low-power mode and all internal states are reset. On initial power-up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in Hardware mode with multiple CS8420 devices, where synchronization between devices is important. INT - Interrupt Output The INT output pin indicates errors and key events during the operation of the CS8420. All bits affecting INT are maskable via control registers. The condition(s) that initiated interrupt are readable via a control register. The polarity of the INT output, as well as selection of a standard or open-drain output, is set via a control register. Once set true, the INT pin goes false only after the interrupt status registers have been read, and the interrupt status bits have returned to zero.
Audio Input Interface:
SDIN - Serial Audio Input Port Data Input Audio data serial input pin. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi)
AES3/SPDIF Receiver Interface:
RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3-type data. RERR - Receiver Error Indicator When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go high are: validity, parity error, bi-phase coding error, confidence, QCRC and CCRC errors, as well as loss of lock in the PLL. Optionally, each condition may be masked from affecting the RERR pin using the Receiver Error Mask Register. The RERR pin tracks the status of the unmasked errors: the pin goes high as soon as an unmasked error occurs and goes low immediately when all unmasked errors go away.
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EMPH - Pre-Emphasis Indicator Output EMPH is low when the incoming AES3 data indicates the presence of 50/15 s pre-emphasis. When the AES3 data indicates the absence of pre-emphasis or the presence of other than 50/15 s pre-emphasis EMPH is high. This is also a start-up option pin, and requires a 47 k resistor to either VD+ or DGND, which determines the AD2 address bit for the control port in IC mode.
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso)
AES3/SPDIF Transmitter Interface:
TCBL - Transmit Channel Status Block Start This pin can be configured as an input or output. When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK (or RMCK, depending on which clock is operating the AES3 encoder block) clocks will cause the next transmitted sub-frame to be the start of a channel status block. TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state.
Control Port Signals:
SCL/CCLK - Control Port Clock SCL/CCLK is the serial control interface clock, and is used to clock control data bits into and out of the CS8420. AD0/CS - Address Bit 0 (IC) / Control Port Chip Select (SPI) A falling edge on this pin puts the CS8420 into SPI Control Port mode. With no falling edge, the CS8420 defaults to IC mode. In IC mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the CS8420. AD1/CDIN - Address Bit 1 (IC) / Serial Control Data In (SPI) In IC mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port interface SDA/CDOUT - Serial Control Data I/O (IC) / Data Out (SPI) In IC mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VD+. In SPI mode, CDOUT is the output data from the control port interface on the CS8420.
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Miscellaneous Pins:
U - User Data The U pin may optionally be used to input User data for transmission by the AES3 transmitter (see Figure 20 for timing information). Alternatively, the U pin may be set to output User data from the AES3 receiver (see Figure 19 for timing information). If not driven, a 47 k pull-down resistor is recommended for the U pin since the default state of the UD direction bit sets the U pin as an input. The pull-down resistor ensures that the transmitted user data will be zero. If the U pin is always set to be an output, thereby causing the U bit manager to be the source of the U data, the resistor is not necessary. The U pin should not be tied directly to ground in case it is programmed to be an output and subsequently tries to output a logic high. This situation may affect the long-term reliability of the device. If the U pin is driven by a logic level output, a 100 series resistor is recommended.
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CS8420 13. HARDWARE MODES
13.1 Overall Description
The CS8420 has six Hardware modes, which allow use of the device without using a micro-controller to access the device control registers and CS & U data. The flexibility of the CS8420 is necessarily limited in Hardware mode. Various pins change function in Hardware mode, and various data paths are also possible. These alternatives are identified by Hardware mode numbers 1 through 6. The following sections describe the data flows and pin definitions for each Hardware mode.
13.1.1 Hardware Mode Definitions
Hardware mode is selected by connecting the H/S pin to `1'. In Hardware mode, 3 pins (DFC0, DFC1 & S/AES) determine the Hardware mode number, according to Table 5. Start-up options are used extensively in Hardware mode. Options include whether the serial audio output ports are master or slave, the serial audio ports' format and whether TCBL is an input or an output. Which output pins are used to set which modes depends on which Hardware mode is being used. DFC1 DFC0 S/AES
0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 1
Hardware Mode Number
1 - Default Data Flow, AES3 input 2 - Default Data Flow, serial input 3 - Transceive Flow, with SRC 4 - Transceive Flow, no SRC 5 - AES3 Rx only, AES3 input 6 - AES3 Tx only, serial input
Table 5. Hardware Mode Definitions
13.1.2 Serial Audio Port Formats
In Hardware mode, only a limited number of alternative serial audio port formats are available. These formats are described by Tables 6 and 7, which define the equivalent Software mode bit settings for each format. Timing diagrams are shown in Figures 17 and 18. For each Hardware mode, the following pages contain a data flow diagram, a pin-out drawing, a pin descriptions list and a definition of the available start-up options. SOSF 0 0 0 0 0 SORES1/0 00 00 00 10 11 SOJUST 0 0 1 0 0 SODEL 0 1 0 1 0 SOSPOL 1 0 0 0 1 SOLRPOL 0 1 0 1 0
OF1 - Left-Justified OF2 - IS 24-bit data OF3 - Right-Justified, Master mode only OF4 - IS 16-bit data OF5 - Direct AES3 data
Table 6. Serial Audio Output Formats Available in Hardware Mode
IF1 - Left-Justified IF2 - IS IF3 - Right-Justified 24-bit data IF4 - Right-Justified 16-bit data
SISF 0 0 0 0
SIRES1/0 00 00 00 10
SIJUST 0 0 1 1
SIDEL 0 1 0 0
SISPOL 1 0 0 0
SILRPOL 0 1 0 0
Table 7. Serial Audio Input Formats Available in Hardware Mode
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13.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input)
Hardware Mode 1 data flow is shown in Figure 24. Audio data is input via the AES3 receiver, and rate converted. The audio data at the new rate is then output both via the serial audio output port and via the AES3 transmitter. The channel status data, user data and validity bit information are handled in four alternative modes: 1A and 1B, determined by a start-up resistor on the COPY pin. In mode 1A, the received PRO, COPY, ORIG, EMPH, and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied from the received channel status data, and the transmitted U and V bits are 0. In mode 1B, only the COPY and ORIG pins are output, and reflect the received channel status data. The transmitted channel status bits, user data and validity bits are input serially via the PRO/C, EMPH/U and AUDIO/V pins. Figure 20 shows the timing requirements. Start-up options are shown in Table 8, and allow choice of the serial audio output port as a master or slave, choice of four serial audio output port formats, and the source for transmitted C, U and V data. The following pages contain the detailed pin descriptions for Hardware mode 1. If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held.
VD+ Output Clock Source OMCK
DFC0
DFC1
S/AES
H/S
Clocked by Input Derived Clock
Clocked by Output Clock
RXP RXN
AES3 Rx & Decoder
Sample Rate Converter
Serial Audio Output AES3 Encoder & Tx
OLRCK OSCLK SDOUT TXP TXN TCBLD
C & U bit Data Buffer
RMCK
RERR MUTE
PRO/C
COPY ORIG EMPH/U AUDIO/V TCBL
Power supply pins (VD+, VA+, DGND, AGND), the reset pin (RST) and the PLL filter pin (FILT) are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 24. Hardware Mode 1 - Default Data Flow, AES3 Input
SDOUT
LO HI -
RMCK
LO LO HI HI
RERR
LO HI LO HI
COPY
LO HI
Function
Serial Output Port is Slave Serial Output Port is Master Mode1A: C transmitted data is copied from received data, U & V = 0, received PRO, EMPH, AUDIO are visible. Mode 1B: CUV transmitted data is input serially on pins, received PRO, EMPH, AUDIO are not visible Serial Output Format OF1 Serial Output Format OF2 Serial Output Format OF3 Serial Output Format OF4
Table 8. Hardware Mode 1 Start-Up Options
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13.2.1 Pin Description - Hardware Mode 1
Overall Device Control:
DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, as shown in Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to ground in Hardware mode 1 in order to select the AES3 input. MUTE - Mute Output Data Input If MUTE is low, audio data is passed normally. If MUTE is high, both the AES3 transmitted audio data and the serial audio output port data is set to digital zero. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso).
AES3/SPDIF Receiver Interface:
RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). This is also a start-up option pin and requires a pull-up or pull-down resistor.
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RERR - Receiver Error Indicator When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase coding error, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor. EMPH/U - Pre-Emphasis Indicator Output or U-Bit Data Input The EMPH/U pin reflects either the state of the EMPH channel status bits in the incoming AES3 type data stream, or is the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. When indicating emphasis, EMPH/U is low if the incoming data indicates 50/15 s pre-emphasis and high otherwise. COPY - Copy Channel Status Bit Output The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. This is also a start-up option pin, and requires a pull-up or pull-down resistor. ORIG - Original Channel Status Output SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicates that the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. PRO/C - Professional Channel Status Bit Output or C-Bit Data Input The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 type data stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by OLRCK. AUDIO/V - Audio Channel Status Bit Output or V-Bit Data Input The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type data stream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by OLRCK.
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso)
AES3/SPDIF Transmitter Interface:
TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the current transmitted sub-frame to be the start of a channel status block. TCBLD - Transmit Channel Status Block Direction Input Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input. TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. 58 DS245F4
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13.3 Hardware Mode 2 Description
(DEFAULT Data Flow, Serial Input) Hardware Mode 2 data flow is shown in Figure 25. Audio data is input via the serial audio input port, and rate converted. The audio data at the new rate is then output both via the serial audio output port and via the AES3 transmitter. The C, U, and V bits in the AES3 output stream may be set in two methods, selected by the CUVEN pin. When CUVEN is low, mode 2A is selected, where COPY/C, ORIG/U, and EMPH/V pins allow selected channel status data bits to be set. The COPY and ORIG pins are used to set the pro bit, the copy bit, and the L bit, as shown in Table 9. In consumer mode, the transmitted category code shall be 0101100b, which indicates sample rate converter. The transmitted U and V bits are zero.When the CUVEN pin is high, mode 2B is selected, where COPY/C, ORIG/U, and EMPH/V become serial bit inputs for C, U, and V data. This data is clocked by both edges of OLRCK, and the channel status block start is indicated or determined by TCBL. Figure 20 shows the timing requirements. Audio serial port data formats are selected as shown in Tables 6, 7 and 10. Start-up options are shown in Table 11, and allow choice of the serial audio output port as a master or slave and whether TCBL is an input or an output. The serial audio input port is always a slave.
VD+
VD+
Output Clock Source OMCK
DFC0
DFC1
S/AES
H/S
Clocked by Input Derived Clock
Clocked by Output Clock
ILRCK ISCLK SDIN
Serial Audio Input
Sample Rate Converter
Serial Audio Output AES3 Encoder & Tx
OLRCK OSCLK SDOUT TXP TXN
C & U bit Data Buffer
RMCK
LOCK SFMT1 SFMT0 COPY/C ORIG/U EMPH/V CUVEN TCBL
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT) are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 25. Hardware Mode 2 - Default Data Flow, Serial Audio Input
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COPY/C
0 0 1 1
ORIG/U
0 1 0 1
Function PRO=0, COPY=0, L=0 PRO=0, COPY=0, L=1 PRO=0, COPY=1, L=0 PRO=1
Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function
SFMT1
0 0 1 1
SFMT0
0 1 0 1
Function Serial Input & Output Format IF1&OF1 Serial Input & Output Format IF2&OF2 Serial Input & Output Format IF3&OF3 Serial Input & Output Format IF4&OF3
Table 10. HW Mode 2 Serial Audio Port Format Selection
SDOUT
LO HI -
LOCK LO HI
Function Serial Output Port is Slave Serial Output Port is Master TCBL is an input TCBL is an output
Table 11. Hardware Mode 2 Start-Up Options
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13.3.1 Pin Description - Hardware Mode 2
Overall Device Control:
DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to VD+ in Hardware mode 2, in order to select the serial audio input. SFMT0, SFMT1 - Serial Audio Port Data Format Select Inputs SFMT0 and SFMT1 select the serial audio input and output ports' format. See Table 10. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso).
Audio Input Interface:
SDIN - Serial Audio Input Port Data Input Audio data serial input pin. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi)
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RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). LOCK - PLL Lock Indicator Output LOCK low indicates that the PLL is locked. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso).
AES3/SPDIF Transmitter Interface:
TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the current transmitted sub-frame to be the start of a channel status block. CUVEN - C, U and V bit Input Enable Mode Input The CUVEN pin determines how the channel status data, user data and validity bit is input. When CUVEN is low, Hardware mode 2A is selected, where the EMPH/V, COPY/C and ORIG/U pins are used to enter selected channel status data. When CUVEN is high, hardware 2B is selected, where the EMPH/V, COPY/C and ORIG/U pins are used to enter serial C, U and V data. EMPH/V - Pre-Emphasis Indicator Input or V Bit Input In mode 2A, EMPH/V low sets the 3 EMPH channel status bits to indicate 50/15 s pre-emphasis. EMPH/V high sets the 3 EMPH bits to 000 indicating no pre-emphasis. In mode 2B, EMPH/V low sets the V bit to indicate valid audio. EMPH/V high sets the V-bit to indicate non-valid audio. COPY/C - COPY Channel Status Bit Input or C Bit Input In mode 2A, the COPY/C pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3 type data stream (See Table 9). In mode 2B, COPY/C becomes the direct C bit input data pin. ORIG/U - ORIG Channel Status Bit Input or U Bit Input In mode 2A, the ORIG/U pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3 type data stream. (See Table 9). In mode 2B, ORIG/U becomes the direct U bit input data pin.
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13.4 Hardware Mode 3 Description
(Transceive Data Flow, with SRC) Hardware Mode 3 data flow is shown in Figure 26. Audio data is input via the AES3 receiver, and rate converted. The audio data at the new rate is then output via the serial audio output port. Different audio data, synchronous to OMCK, may be input into the serial audio input port, and output via the AES3 transmitter. The channel status data, user data, and validity bit information are handled in two alternative modes: 3A and 3B, determined by a start-up resistor on the COPY pin. In mode 3A, the received PRO, COPY, ORIG, and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied from the received channel status data, and the transmitted U and V bits are zero. In mode 3B, only the COPY, and ORIG pins are output, and reflect the received channel status data. The transmitted channel status bits, user data, and validity bits are input serially via the PRO/C, EMPH/U, and AUDIO/V pins. Figure 20 shows the timing requirements. The serial audio input port is always a slave. If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held. Start-up options are shown in Table 12, and allow choice of the serial audio output port as a master or slave, whether TCBL is an input or an output, the serial audio ports formats, and the source of the transmitted C, U, and V data. The following pages contain the detailed pin descriptions for Hardware mode 3.
VD+
VD+ OSCLK ISCLK SDOUT OLRCK ILRCK SDIN
Output Clock Source OMCK
DFC0
DFC1
H/S
Clocked by Input Derived Clock
Clocked by Output Clock
Serial Audio Output
Serial Audio Input AES3 Encoder & Tx TXP TXN
RXP RXN
AES3 Rx & Decoder
Sample Rate Converter
C & U bit Data Buffer
RMCK RERR
PRO/C COPY ORIG EMPH/U AUDIO/V TCBL
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT) are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 26. Hardware Mode 3 - Transceive Data Flow, with SRC
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SDOUT RMCK RERR ORIG COPY Function LO Serial Output Port is Slave HI Serial Output Port is Master LO Mode 3A: C transmitted data is copied from received data, U & V =0, received PRO, EMPH, AUDIO is visible HI Mode 3B: CUV transmitted data is input serially on pins, received PRO, EMPH and AUDIO is not visible LO LO Serial Input & Output Format IF1&OF1 LO HI Serial Input & Output Format IF2&OF2 HI LO Serial Input & Output Format IF3&OF3 HI HI Serial Input & Output Format IF2&OF4 LO TCBL is an input HI TCBL is an output
Table 12. Hardware Mode 3 Start-Up Options
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13.4.1 Pin Description - Hardware Mode 3
Overall Device Control:
DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso).
Audio Input Interface:
SDIN - Serial Audio Input Port Data Input Audio data serial input pin. This data will be transmitted out the AES3 port. ISCLK - Serial Audio Input Port Bit Clock Input Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input Word rate clock for the audio data on the SDIN pin. The frequency will be at the output sample rate (Fso)
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin.
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OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso).
AES3/SPDIF Transmitter Interface:
TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the current transmitted sub-frame to be the start of a channel status block.
AES3/SPDIF Receiver Interface:
RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). This is also a start-up option pin, and requires a pull-up or pull-down resistor. RERR - Receiver Error Indicator Output When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase coding error, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor. EMPH/U - Pre-emphasis Indicator Output or U-Bit Data Input The EMPH/U pin either reflects the state of the EMPH channel status bits in the incoming AES3 type data stream, or is the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. If indicating emphasis EMPH/U is low when the incoming data indicates 50/15 s pre-emphasis and high otherwise. COPY - Copy Channel Status Bit Output The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. This is also a start-up option pin, and requires a pull-up or pull-down resistor. ORIG - Original Channel Status Output SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicates that the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. This is also a start-up option pin, and requires a pull-up or pull-down resistor. PRO/C - Professional Channel Status Bit Output or C-Bit Data Input The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 type data stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by OLRCK. AUDIO/V - Audio Channel Status Bit Output or V-Bit Data Input The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type data stream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by OLRCK.
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13.5 Hardware Mode 4 Description
(Transceive Data Flow, No SRC) Hardware mode 4 data flow is shown in Figure 27. Audio data is input via the AES3 receiver, and routed to the serial audio output port. Different audio data synchronous to RMCK may be input into the serial audio input port, and output via the AES3 transmitter. The channel status data, user data, and validity bit information are handled in two alternative modes: 4A and 4B, determined by a start-up resistor on the COPY pin. In mode 4A, the received PRO, COPY, ORIG, EMPH, and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied from the received channel status data, and the transmitted U and V bits are 0. In mode 4B, only the COPY and ORIG pins are output, and reflect the received channel status data. The transmitted channel status bits, user data, and validity bits are input serially via the PRO/C, EMPH/U, and AUDIO/V pins. Figure 20 shows the timing requirements. The APMS pin allows the serial audio input port to be set to master or slave. If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodified to the serial audio output port. Start-up options are shown in Table 13, and allow choice of the serial audio output port as a master or slave, whether TCBL is an input or an output, the audio serial ports formats, and the source of the transmitted C, U, and V data. The following pages contain the detailed pin descriptions for Hardware mode 4.
VD+
VD+ OSCLK ISCLK SDOUT OLRCK ILRCK SDIN
DFC0
DFC1
H/S
Serial Audio Output RXP RXN AES3 Rx & Decoder
Serial Audio Input AES3 Encoder & Tx
APMS
TXP TXN
C & U bit Data Buffer
RMCK
RERR
PRO/C COPY ORIG EMPH/U AUDIO/V
TCBL
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT) are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 27. Hardware Mode 4 - Transceive Data Flow, Without SRC
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SDOUT RMCK RERR ORIG COPY Function LO Serial Output Port is Slave HI Serial Output Port is Master LO Mode 4A: C transmitted data is copied from received data, U & V =0, received PRO, EMPH, AUDIO is visible HI Mode 4B: CUV transmitted data is input serially on pins, received PRO, EMPH and AUDIO is not visible LO LO Serial Input & Output Format IF1&OF1 LO HI Serial Input & Output Format IF2&OF2 HI LO Serial Input & Output Format IF3&OF3 HI HI Serial Input & Output Format IF1&OF5 LO TCBL is an input HI TCBL is an output
Table 13. Hardware Mode 4 Start-Up Options
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13.5.1 Pin Description - Hardware Mode 4
Overall Device Control:
DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5.
Audio Input Interface:
SDIN - Serial Audio Input Port Data Input Audio data serial input pin. This data will be transmitted out the AES3 port. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi) APMS - Serial Audio Input Port Master or Slave APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to set the port as a slave.
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
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OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi).
AES3/SPDIF Transmitter Interface:
TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three RMCK clocks will cause the current transmitted sub-frame to be the start of a channel status block.
AES3/SPDIF Receiver Interface:
RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). This is also a start-up option pin, and requires a pull-up or pull-down resistor. RERR - Receiver Error Indicator Output When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase coding error, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor. EMPH/U - Pre-emphasis Indicator Output or U-Bit Data Input The EMPH/U pin either reflects the state of the EMPH channel status bit in the incoming AES3 type data stream, or is the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. If indicating emphasis EMPH/U is high when the incoming data indicates 50/15 s pre-emphasis and low otherwise. COPY - Copy Channel Status Bit Output The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. This is also a start-up option pin, and requires a pull-up or pull-down resistor. ORIG - Original Channel Status Output SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicates that the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. This is also a start-up option pin, and requires a pull-up or pull-down resistor. PRO/C - Professional Channel Status Bit Output or C-Bit Data Input The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 type data stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by OLRCK. AUDIO/V - Audio Channel Status Bit Output or V-Bit Data Input The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type data stream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by OLRCK. 70 DS245F4
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13.6 Hardware Mode 5 Description
(AES3 Receiver Only) Hardware Mode 5 data flow is shown in Figure 28. Audio data is input via the AES3 receiver, and routed to the serial audio output port. The PRO, COPY, ORIG, EMPH, and AUDIO channel status bits are output on pins. The decoded C and U bits are also output, clocked by both edges of OLRCK (Master mode only, see Figure 19). If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodified to the serial audio output port. Start-up options are shown in Table 14, and allow choice of the serial audio output port as a master or slave, and the serial audio port format. The following pages contain the detailed pin descriptions for Hardware mode 5.
VD+
VD+
VD+
DFC0
DFC1
S/AES
H/S OMCK
RXP RXN
AES3 Rx & Decoder
Serial Audio Output
OLRCK OSCLK SDOUT
C & U bit Data Buffer
C U
RMCK
RERR NVERR CHS COPY ORIG EMPH PRO AUDIO RCBL
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT) are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 28. Hardware Mode 5 - AES3 Receiver Only
SDOUT
LO HI -
ORIG
LO LO HI HI
EMPH
LO HI LO HI
Function
Serial Output Port is Slave Serial Output Port is Master Serial Output Format OF1 Serial Output Format OF2 Serial Output Format OF3 Serial Output Format OF5
Table 14. Hardware Mode 5 Start-Up Options
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13.6.1 Pin Description - Hardware Mode 5
Overall Device Control:
DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to DGND in Hardware mode 5, in order to select the AES3 input. OMCK - Output Section Master Clock Input Output section master clock input. This pin is not used in this mode and should be connected to DGND.
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi).
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AES3/SPDIF Receiver Interface:
RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). RERR - Receiver Error Indicator When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: validity, parity error, and bi-phase coding error, as well as loss of lock in the PLL. NVERR - No Validity Receiver Error Indicator When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per frame of incoming AES3 data. Conditions that cause NVERR to go high are: parity error, and bi-phase coding error, as well as loss of lock in the PLL. EMPH - Pre-emphasis Indicator Output EMPH is low when the incoming AES3 data indicates the presence of 50/15 s pre-emphasis. When the AES3 data indicates the absence of pre-emphasis or the presence of non 50/15 s pre-emphasis EMPH is high. This is also a start-up option pin, and requires a pull-up or pull-down resistor. COPY - Copy Channel Status Bit Output The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. ORIG - Original Channel Status Output SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicates that the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. This is also a start-up option pin, and requires a pull-up or pull-down resistor. PRO - Professional Channel Status Bit Output The PRO pin reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 type data stream. AUDIO - Audio Channel Status Bit Output The AUDIO pin reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type data stream. RCBL - Receiver Channel Status Block Output RCBL indicates the beginning of a received channel status block. RCBL goes high 2 frames after the reception of a Z preamble, remains high for 16 frames while COPY, ORIG, AUDIO, EMPH and PRO are updated, and returns low for the remainder of the block. RCBL changes on rising edges of RMCK. CHS - Channel Select Input Selects which sub-frame's channel status data is output on the EMPH, COPY, ORIG, PRO and AUDIO pins. Channel A is selected when CHS is low, channel B is selected when CHS is high. U - User Data Output The U pin outputs user data from the AES3 receiver, clocked by rising and falling edges of OLRCK. C - Channel Status Data Output The C pin outputs channel status data from the AES3 receiver, clocked by rising and falling edges of OLRCK. DS245F4 73
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13.7 Hardware Mode 6 Description
(AES3 Transmitter Only) Hardware Mode 6 data flow is shown in Figure 29. Audio data is input via the serial audio input port and routed to the AES3 transmitter. The transmitted channel status, user, and validity data may be input in two alternative methods, determined by the state of the CEN pin. Mode 6A is selected when the CEN pin is low. In mode 6A, the user data and validity bit are input via the U and V pins, clocked by both edges of ILRCK. The channel status data is derived from the state of the COPY/C, ORIG, EMPH, and AUDIO pins. Table 15 shows how the COPY/C and ORIG pins map to channel status bits. In consumer mode, the transmitted category code shall be set to Sample Rate Converter (0101100b). Mode 6B is selected when the CEN pin is high. In mode 6B, the channel status, user data and validity bit are input serially via the COPY/C, U, and V pins. These pins are clocked by both edges of ILRCK (if the port is in Master mode). Figure 20 shows the timing requirements. The channel status block pin (TCBL) may be an input or an output, determined by the state of the TCBLD pin. The serial audio input port data format is selected as shown in Table 15, and may be set to master or slave by the state of the APMS input pin. The following pages contain detailed pin descriptions for Hardware mode 6.
VD+
VD+
VD+
VD+
Output Clock Source FILT OMCK
DFC0
DFC1
S/AES
H/S
ILRCK ISCLK SDIN
Serial Audio Input
AES3 Encoder & Tx
TXP TXN
C, U, V Data Buffer
CEN U V
APMS SFMT1 SFMT0
COPY/C ORIG EMPH AUDIO TCBL TCBLD
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 29. Hardware Mode 6 - AES3 Transmitter Only
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COPY/C
0 0 1 1
ORIG
0 1 0 1
Function PRO=0, COPY=0, L=0 PRO=0, COPY=0, L=1 PRO=0, COPY=1, L=0 PRO=1
Table 15. HW 6 COPY/C and ORIG Pin Function
SFMT1
0 0 1 1
SFMT0
0 1 0 1
Function Serial Input Format IF1 Serial Input Format IF2 Serial Input Format IF3 Serial Input Format IF4
Table 16. HW 6 Serial Port Format Selection
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13.7.1 Pin Description - Hardware Mode 6
COPY/C DFC0 EMPH SFMT0 SFMT1 VA+ AGND FILT RST APMS TCBLD ILRCK ISCLK SDIN
1 2 3 4 5 6* 7* 8* 9* 10 11 12 13 14
28 27 26 25 *24 *23 *22 21 20 19 18 17 16 15
ORIG DFC1 TXP TXN H/S VD+ DGND OMCK S/AES AUDIO U V CEN TCBL
* Pins which remain the same function in all modes.
Overall Device Control:
DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to VD+ in Hardware mode 6, in order to select the serial audio input. SFMT0, SFMT1 - Serial Audio Input Port Data Format Select Inputs SFMT0 and SFMT1 select the serial audio input port format. See Table 15. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso).
Audio Input Interface:
SDIN - Serial Audio Input Port Data Input Audio data serial input pin. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin.
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ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. APMS - Serial Audio Input Port Master or Slave. APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to set the port as a slave.
AES3/SPDIF Transmitter Interface:
TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the current transmitted sub-frame to be the start of a channel status block. TCBLD - Transmit Channel Status Block Direction Input Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input. EMPH - Pre-Emphasis Indicator Input In mode 6B, EMPH pin low sets the 3 EMPH channel status bits to indicate 50/15 s pre-emphasis. If EMPH is high the 3 EMPH channel status bits are set to 000 indicating no pre-emphasis. COPY/C - COPY Channel Status Bit Input or C Bit Input In mode 6B, the COPY/C pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3 type data stream (See Table 15). In mode 6A, the COPY/C pin becomes the direct C bit input data pin. ORIG - ORIG Channel Status Bit Input In mode 6B, the ORIG pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3 type data stream. See Table 15. AUDIO - Audio Channel Status Bit Input In mode 6B, the AUDIO pin determines the state of the audio/non audio Channel Status bit in the outgoing AES3 type data stream. V - Validity Bit Input In modes 6A and 6B, the V pin input determines the state of the validity bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. U - User Data Bit Input In modes 6A and 6B, the U pin input determines the state of the user data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. CEN - C Bit Input Enable Mode Input The CEN pin determines how the channel status data bits are input. When CEN is low, Hardware mode 6A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected channel status data. When CEN is high, Hardware mode 6B is selected, where the COPY/C pin is used to enter serial channel status data. DS245F4 77
CS8420 14. EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPONENTS
This section details the external components required to interface the AES3 transmitter and receiver to cables and fiber-optic components.
14.1
AES3 Transmitter External Components
The output drivers on the CS8420 are designed to drive both the professional and consumer interfaces. The AES3 specification for professional/broadcast use calls for a 110 source impedance and a balanced drive capability. Since the transmitter output impedance is very low, a 110 resistor should be placed in series with one of the transmit pins. The specifications call for a balanced output drive of 2-7 volts peak-to-peak into a 110 load with no cable attached. Using the circuit in Figure 30, the output of the transformer is shortcircuit protected, has the proper source impedance, and provides a 5 volts peak-to-peak signal into a 110 load. Lastly, the two output pins should be attached to an XLR connector with male pins and a female shell, and with pin 1 of the connector grounded.
CS8420 TXP XLR TXN 110-(RTXP+RTXN)
1
Figure 30. Professional Output Circuit
In the case of consumer use, the IEC60958 specifications call for an unbalanced drive circuit with an output impedance of 75 and a output drive level of 0.5 V peak-to-peak 20% when measured across a 75 load using no cable. The circuit shown in Figure 31 only uses the TXP pin and provides the proper output impedance and drive level using standard 1% resistors. The connector for a consumer application would be an RCA phono socket. This circuit is also short circuit protected.
CS8420 TXP 90.9 TXN RCA Phono 374-RTXP
Figure 31. Consumer Output Circuit
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The TXP pin may be used to drive TTL or CMOS gates as shown in Figure 32. This circuit may be used for optical connectors for digital audio since they usually have TTL or CMOS compatible inputs. This circuit is also useful when driving multiple digital audio outputs since RS422 line drivers have TTL compatible inputs.
CS8420 TXP TTL or CMOS Gate TXN
Figure 32. TTL/CMOS Output Circuit
14.2
AES3 Receiver External Components
The CS8420 AES3 receiver is designed to accept both the professional and consumer interfaces. The digital audio specifications for professional use call for a balanced receiver, using XLR connectors, with 110 20% impedance. The XLR connector on the receiver should have female pins with a male shell. Since the receiver has a very high input impedance, a 110 resistor should be placed across the receiver terminals to match the line impedance, as shown in Figure 33. Although transformers are not required by the AES, they are, however, strongly recommended.
XLR 110 Twisted Pair 1 * See Text 110 RXN CS8420 RXP
Figure 33. Professional Input Circuit
If some isolation is desired without the use of transformers, a 0.01 F capacitor should be placed in series with each input pin (RXP and RXN) as shown in Figure 34. However, if a transformer is not used, high frequency energy could be coupled into the receiver, causing degradation in analog performance.
XLR 110 Twisted Pair 1 110 0.01 F RXN * See Text 0.01 F CS8420 RXP
Figure 34. Transformerless Professional Input Circuit
Figures 33 and 34 show an optional DC blocking capacitor (0.1 F to 0.47 F) in series with the cable input. This improves the robustness of the receiver, preventing the saturation of the transformer, or any DC current flow, if a DC voltage is present on the cable. In the configuration of systems, it is important to avoid ground loops and DC current flowing down the shield of the cable that could result when boxes with different ground potentials are connected. Generally, it is good practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capacitor to chassis ground at the receiver. However, in some cases it is advantageous to have the ground of two boxes held to the same potential, and the cable shield might be depended upon to make that electrical
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connection. Generally, it may be a good idea to provide the option of grounding or capacitively coupling the shield to the chassis. In the case of the consumer interface, the standards call for an unbalanced circuit having a receiver impedance of 75 5%. The connector for the consumer interface is an RCA phono socket. The receiver circuit for the consumer interface is shown in Figure 35.
RCA Phono 75 Coax 75 RXN 0.01 F 0.01 F CS8420 RXP
Figure 35. Consumer Input Circuit
The circuit shown in Figure 36 may be used when external RS422 receivers, optical receivers or other TTL/CMOS logic outputs drive the CS8420 receiver section.
TTL/CMOS Gate 0.01 F CS8420 RXP
0.01 F
RXN
Figure 36. TTL/CMOS Input Circuit
14.3
Isolating Transformer Requirements
The transformer should be capable of operating from 1.5 to 14 MHz, which is equivalent to an audio data rate of 25 kHz to 108 kHz after bi-phase mark encoding. Transformers provide isolation from ground loops, 60 Hz noise, and common mode noise and interference. One of the important considerations when choosing transformers is minimizing shunt capacitance between primary and secondary windings. The higher the shunt capacitance, the lower the isolation between primary and secondary, and the more coupling of high frequency energy. This energy appears in the form of common mode noise on the receive side ground and has the potential to degrade analog performance. Therefore, for best performance, shielded transformers optimized for minimum shunt capacitance should be used. See Application Note 134 for a selection of manufacturers and their part numbers.
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CS8420 15. CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT
The CS8420 has a comprehensive channel status (C) and user (U) data buffering scheme, which allows automatic management of channel status blocks and user data. Alternatively, sufficient control and access is provided to allow the user to completely manage the C and U data via the control port.
15.1
AES3 Channel Status(C) Bit Management
The CS8420 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits), and also 384 bits of U information. The user may read from or write to these RAMs via the control port. Unlike the audio data, it is not possible to 'sample-rate' convert the C bits. This is because specific meanings are associated with fixed-length data patterns, which should not be altered. Since the output data rate of the CS8420 will differ from the input rate when sample-rate conversion is done, it is not feasible to directly transfer incoming C data to the output. The CS8420 manages the flow of channel status data at the block level, meaning that entire blocks of channel status information are buffered at the input, synchronized to the output timebase, and then transmitted. The buffering scheme involves a cascade of three block-sized buffers, named D,E, and F as shown in Figure 37. The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control port address 20h) is the consumer/professional bit for channel status block A.
A 8-bits From AES3 Receiver B 8-bits
D
Received Data Buffer
E
24 words
F
Transmit Data Buffer
To AES3 Transmitter
Control Port
Figure 37. Channel Status Data Buffer Structure
The first buffer, D, accepts incoming C data from the AES receiver. The 2nd buffer, E, accepts entire blocks of data from the D buffer. The E buffer is also accessible from the control port, allowing read and writing of the C data. The 3rd buffer (F) is used as the source of C data for the AES3 transmitter. The F buffer accepts block transfers from the E buffer. If the input rate is slower than the output rate (so that in a given time interval, more channel status blocks are transmitted than received), some buffered C blocks will be transmitted multiple times. If the input rate is faster than the output rate, some will not be transmitted at all. This is illustrated in (Figure 38). In this manner, channel status block integrity is maintained. If the transmitted sample count bits are important in the application, then they will need to be updated via the control port by the microcontroller for every outgoing block.
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15.1.1 Manually Accessing the E Buffer
The user can monitor the data being transferred by reading the E buffer, which is mapped into the register space of the CS8420, via the control port. The user can modify the data to be transmitted by writing to the E buffer.
Fso > Fsi (3/2) Causes blocks 1 and 3 to be transmitted twice Contents of E buffer Updated at Fsi rate Contents of F buffer Updated from E Output at Fso rate block 1 block 1 block 2 block 1 block 2 block 3 block 3 block 3 block 4 block 4 block 5 block 5
Fso < Fsi (2/3) Causes blocks 3 and 6 to not be transmitted Contents of E buffer Updated at Fsi rate Contents of F buffer Updated from E Output at Fso rate block 1 block 1 block 2 block 3 block 2 block 4 block 4 block 5 block 6 block 5 block 7 block 7
Figure 38. Channel Status Block Handling When Fso is Not Equal to Fsi
The user can configure the interrupt enable register to cause interrupts to occur whenever D-to-E or E-toF buffer transfers occur. This allows determination of the allowable time periods to interact with the E buffer. Also provided are D-to-E and E-to-F inhibit bits. The associated buffer transfer is disabled whenever the user sets these bits. These may be used whenever "long" control port interactions are occurring. They can also be used to align the behavior of the buffers with the selected audio data flow. For example, if the audio data flow is serial port in to AES3 out, then it is necessary to inhibit D-to-E transfers, since these would overwrite the desired transmit C data with invalid data. Flowcharts for reading and writing to the E buffer are shown in Figures 39 and 40. For reading, since a Dto-E interrupt just occurred, then there a substantial time interval until the next D-to-E transfer (approximately 192 frames worth of time). This is usually plenty of time to access the E data without having to inhibit the next transfer. For writing, the sequence starts after a E-to-F transfer, which is based on the output timebase. Since a D-to-E transfer could occur at any time (this is based on the input timebase), then it is important to inhibit D-to-E transfers while writing to the E buffer until all writes are complete. Then wait until the next E-to-F transfer occurs before enabling D-to-E transfers. This ensures that the data written to the E buffer actually gets transmitted and not overwritten by a D-to-E transfer. If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calculated by the CS8420, and does not have to be written into the last byte of the block by the host microcontroller.
D to E interrupt occurs Optionally set D to E inhibit Read E data If set, clear D to E inhibit Return
Figure 39. Flowchart for Reading the E Buffer
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E to F interrupt occurs Optionally set E to F inhibit Set D to E inhibit Write E data If set, clear E to F inhibit Wait for E to F transfer Clear D to E inhibit Return
Figure 40. Flowchart for Writing the E Buffer
15.1.2 Reserving the First 5 Bytes in the E Buffer
D-to-E buffer transfers periodically overwrite the data stored in the E buffer. This can be a problem for users who want to transmit certain channel status settings which are different from the incoming settings. In this case, the user would have to superimpose his settings on the E buffer after every D-to-E overwrite. To avoid this problem, the CS8420 has the capability of reserving the first 5 bytes of the E buffer for user writes only. When this capability is in use, internal D-to-E buffer transfers will NOT affect the first 5 bytes of the E buffer. Therefore, the user can set values in these first 5 E bytes once, and the settings will persist until the next user change. This mode is enabled via the Channel Status Data Buffer Control register.
15.1.3 Serial Copy Management System (SCMS)
In Software mode, the CS8420 allows read/modify/write access to all the channel status bits. For Consumer mode SCMS compliance, the host microcontroller needs to read and manipulate the Category Code, Copy bit and L bit appropriately. In Hardware mode, the SCMS protocol can be followed by either using the COPY and ORIG input pins, or by using the C bit serial input pin. These options are documented in the Hardware mode section of this data sheet (See "Hardware Modes" on page 55)
15.1.4 Channel Status Data E Buffer Access
The E buffer is organized as 24 x 16-bit words. For each word the MS Byte is the A channel data, and the LS Byte is the B channel data (see Figure 37). There are two methods of accessing this memory, known as one-byte mode and two-byte mode. The desired mode is selected via a control register bit.
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15.1.5 One-Byte Mode
In many applications, the channel status blocks for the A and B channels will be identical. In this situation, if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel will be the same. Similarly, if the user wrote a byte to one channel's block, it would be necessary to write the same byte to the other block. One-Byte mode takes advantage of the often identical nature of A and B channel status data. When reading data in one-byte mode, a single byte is returned, which can be from channel A or B data, depending on a register control bit. If a write is being done, the CS8420 expects a single byte to be input to its control port. This byte will be written to both the A and B locations in the addressed word. One-Byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes' worth of information in 1 byte's worth of access time. If the control port's auto-increment addressing is used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently.
15.1.6 Two-Byte Mode
There are those applications in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, Two-Byte mode should be used to access the E buffer. In this mode, a read will cause the CS8420 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two bytes must now be input to the CS8420's control port. The A channel status data is first, B channel status data second.
15.2
AES3 User (U) Bit Management
The CS8420 U bit manager has four operating modes: Mode 1. Transmit all zeros Mode 2. Block mode Mode 3. Reserved Mode 4. IEC Consumer B
15.2.1 Mode 1: Transmit All Zeros
Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents or U data embedded in an input AES3 data stream. This mode is intended for the user who does not want to transceive U data, and simply wants the output U channel to contain no data.
15.2.2 Mode 2: Block Mode
Mode 2 is very similar to the scheme used to control the C bits. Entire blocks of U data are buffered from input to output, using a cascade of three block-sized RAMs to perform the buffering. The user has access to the second of these three buffers, denoted the E buffer, via the control port. Block mode is designed for use in AES3 in, AES3 out situations in which input U data is decoded using a microcontroller via the control port. It is also the only mode in which the user can merge his/her own U data into the transmitted AES3 data stream. The U buffer access only operates in Two-Byte mode, since there is no concept of A and B blocks for user data. The arrangement of the data in the each byte is that the MSB is the first received bit and is the first 84 DS245F4
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transmitted bit. The first byte read is the first byte received, and the first byte sent is the first byte transmitted.
15.2.3 IEC60958 Recommended U Data Format for Consumer Applications
Modes (3) and (4) are intended for use in AES3 in, AES3 out situations, in which the input U data is formatted as recommended in the "IEC60958 Digital Audio Interface, part 3: Consumer applications" document. In this format, "messages" are formed in the U data from Information Units or IUs. An IU is 8 bits long, and the MSB is always 1, and is called the start bit, or 'P' bit. The remaining 7-bits are called Q, R, S, T, U, V, & W, and carry the desired data. A "message" consists of 3 to 129 IUs. Multiple IUs are considered to be in the same message if they are separated by 0 to 8 zeros, denoted here as filler. A filler sequence of nine or more zeros indicates an intermessage gap. The desired information is normally carried in the sequence of corresponding bits in the IUs. For example, the sequential Q bits from each IU make up the Q sub-code data that is used to indicate Compact Disk track information. This data is automatically extracted from the received IEC60958 stream, and is presented in the control port register map space. Where incoming U data is coded in the above format, and needs to be re-transmitted, the data transfer cannot be done using shift registers, because of the different Fsi and Fso sampling clocks. Instead, input data must be buffered in a FIFO structure, and then read out by the AES3 transmitter at appropriate times. Each bit of each IU must be transceived; unlike the audio samples, there can be no sample rate conversion of the U data. Therefore, there are two potential problems: (1) Message Partitioning When Fso > Fsi, more data is transmitted than received per unit time. The FIFO will frequently be completely emptied. Sensible behavior must occur when the FIFO is empty, otherwise, a single incoming message may be erroneously partitioned into multiple, smaller, messages. (2) Overwriting When Fso < Fsi, more data is received than transmitted per unit time. There is a danger of the FIFO becoming completely full, allowing incoming data to overwrite data that has not yet been output through the AES3 transmitter.
15.2.4 Mode (3): Reserved
This mode has been removed. Use IEC Consumer mode B.
15.2.5 Mode (4): IEC Consumer B
In this mode, the partitioning problem is solved by buffering an entire message before starting to transmit it. In this scheme, zero-segments between messages will be expanded when Fso > Fsi, but the integrity of individual messages is preserved. The overwriting problem (when Fso < Fsi) is solved by only storing a portion of the input U data in the FIFO. Specifically, only the IUs themselves are stored (and not the zeros that provide inter-IU and intermessage "filler"). An inter-IU filler segment of fixed length (OF) will be added back to the messages at the FIFO output, where the length of OF is equal to the shortest observed input filler segment (IF). Storing only IUs (and not filler) within the FIFO makes it possible for the slower AES3 transmitter to "catch up" to the faster AES3 receiver as data is read out of the FIFO. This is because nothing is written into the FIFO when long strings of zeros are input to the AES-EBU receiver. During this time of no writing, the DS245F4 85
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transmitter can read out data that had previously accumulated, allowing the FIFO to empty out. If the FIFO becomes completely empty, zeros are transmitted until a complete message is written into the FIFO. Mode 4 is not fail-safe; the FIFO can still get completely full if there isn't enough "zero-padding" between incoming messages. It is up to the user to provide proper padding, as defined below: Minimum padding = (Fsi/Fso - 1)*[8N + (N-1)*IF +9] + 9 where N is the number of IUs in the message, IF is the number of filler bits between each IU, and Fso Fsi. Example 1: Fsi/Fso = 2, N=4, IF=1: minimum proper padding is 53 bits. Example 2: Fsi/Fso = 1, N=4, IF=7: min proper padding is 9 bits. The CS8420 detects when an overwrite has occurred in the FIFO, and synchronously resets the entire FIFO structure to prevent corrupted U data from being merged into the transmitted AES3 data stream. The CS8420 can be configured to generate an interrupt when this occurs. Mode 4 is recommended for properly formatted U data where mode 3 cannot provide acceptable performance, either because of a too-extreme Fsi/Fso ratio, or because it's unacceptable to change the lengths of filler segments. Mode 4 provides error-free performance over the complete range of Fsi/Fso ratios (provided that the input messages are properly zero-padded for Fsi > Fso).
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CS8420 16. PLL FILTER
16.1 General
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure 41 is a simplified diagram of the PLL in CS8420 devices. When the PLL is locked to an AES3 input stream, it is updated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, FS. When the PLL is locked to ILRCK, it is updated at FS so that the duty cycle of the input doesn't affect jitter. There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown in Figure 44 and Figure 45. In addition, the PLL has been designed to use only the preambles of the AES3 stream to provide lock update information to the PLL. This results in the PLL being immune to data-dependent jitter effects because the AES3 preambles do not vary with the data. The PLL has the ability to lock onto a wide range of input sample rates with no external component changes. If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL will only track up to 12.5% from the nominal center sample rate. The nominal center sample rate is the sample rate that the PLL first locks onto upon application of an AES3 data stream or after enabling the CS8420 clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its wide lock range mode and re-acquire a new nominal center sample rate.
INPUT
Phase Comparator and Charge Pump
VCO Rfilt Cfilt Crip
RMCK
/N
Figure 41. PLL Block Diagram
16.2
External Filter Components
16.2.1 General
The PLL behavior is affected by the external filter component values. Figure 5 on page 12 shows the recommended configuration of the two capacitors and one resistor that comprise the PLL filter. In Table 19 and Table 20, the component values shown for the 32 to 96 kHz range have the highest corner frequency jitter attenuation curve, takes the shortest time to lock, and offers the best output jitter performance. The component values shown in Table 18 and Table 20 for the 8 to 96 kHz range allows the lowest input sample rate to be 8 kHz, and increases the lock time of the PLL. Lock times are worst case for an Fsi transition of 96 kHz. DS245F4 87
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16.2.2 Capacitor Selection
The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable inductance to the circuit. Surface mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted close to the FILT pin to minimize trace inductance. For CRIP, a C0G or NPO dielectric is recommended, and for CFILT, an X7R dielectric is preferred. Avoid capacitors with large temperature coefficients, or capacitors with high dielectric constants, that are sensitive to shock and vibration. These include the Z5U and Y5V dielectrics.
16.2.3 Circuit Board Layout
Board layout and capacitor choice affect each other and determine the performance of the PLL. Figure 42 contains a suggested layout for the PLL filter components and for bypassing the analog supply voltage. The 0.1 F bypass capacitor is in a 1206 form factor. RFILT and the other three capacitors are in an 0805 form factor. The traces are on the top surface of the board with the IC so that there is no via inductance. The traces themselves are short to minimize the inductance in the filter path. The VA+ and AGND traces extend back to their origin and are shown only in truncated form in the drawing.
AGND
1000 pF
Crip Rfilt
.1F
Cfilt
Figure 42. Recommended Layout Example
16.3
Component Value Selection
When transitioning from one revision of the part another, component values need to be changed. It is mandatory for customers to change the external PLL component values when transitioning from revision D to revision D1.
16.3.1 Identifying the Part Revision
The first line of the part marking on the package indicates the part number and package type CS8420-xx. Table 17 shows a list of part revisions and their corresponding second line part marking, which indicates what revision the part is. Revision D D1 Pre-October 2002 (10-Digit) Zxxxxxxxxx Rxxxxxxxxx
Table 17. Second Line Part Marking
FILT
VA+
New (12-Digit) ZFBADXxxxxxx RFBAD1xxxxxx
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16.3.2 Locking to the RXP/RXN Receiver Inputs
CS8420 parts that are configured to lock to only the RXP/RXN receiver inputs should use the external PLL component values listed in Table 18 and Table 19. Values listed for the 32 to 96 kHz Fs range will have the highest corner frequency jitter attenuation curve, take the shortest time to lock, and offer the best output jitter performance. Revision D D1 RFILT (k) 0.909 0.4 CFILT (F) 1.8 0.47 CRIP (nF) 33 47 PLL Lock Time (ms) 56 60
Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz
Revision D D1
RFILT (k) 3.0 1.6
CFILT (F) 0.047 0.33
CRIP (nF) 2.2 4.7
PLL Lock Time (ms) 35 35
Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz*
* Parts used in applications that are required to pass the AES3 or IEC60958-4 specification for receiver jitter tolerance should use these component values. Please note that the AES3 and IEC60958 specifications do not have allowances for locking to sample rates less than 32 kHz or for locking to the ILRCK input. Also note that many factors can affect jitter performance in a system. Please follow the circuit and layout recommendations outlined previously.
16.3.3 Locking to the ILRCK Input
CS8420 parts that are configured to lock to the ILRCK input should use the external PLL component values listed in Table 20. Note that parts that need to lock to both ILRCK and RXP/RXN should use these values. Values listed for the 32 to 96 kHz Fs range will have the highest corner frequency jitter attenuation curve, take the shortest time to lock, and offer the best output jitter performance. Revision D D D1 D1 Fs Range RFILT (k) CFILT (F) CRIP (nF) PLL Lock Time (ms) (kHz) 8 to 96 1.3 2.7 62 120 32-96 8 to 96 32-96 5.1 0.3 0.6 0.15 1.0 0.22 3.9 100 22 70 120 70
Table 20. Locking to the ILRCK Input
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16.3.4 Jitter Tolerance
Shown in Figure 43 is the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4 specification. CS8420 parts used with the appropriate external PLL component values (as noted in Table 19) have been tested to pass this template.
Figure 43. Jitter Tolerance Template
16.3.5 Jitter Attenuation
Shown in Figure 44 and Figure 45 are jitter attenuation plots for the various revisions of the CS8420 when used with the appropriate external PLL component values (as noted in Table 19). The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates less than 32 kHz or for locking to the ILRCK input. These specifications state a maximum of 2 dB jitter gain or peaking.
5
5
0
0
-5
Jitter Attenuation (dB) -5
Jitter Attenuation (dB)
10
0
-10
-10
-15
-15
-20
-20 -1 10
10
1
10 Jitter Frequency (Hz)
2
10
3
10
4
10
5
-25 -1 10
10
0
10
1
10 Jitter Frequency (Hz)
2
10
3
10
4
10
5
Figure 44. Revision D Jitter Attenuation
Figure 45. Revision D1 Jitter Attenuation
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CS8420 17. PARAMETER DEFINITIONS
Input Sample Rate (Fsi) The sample rate of the incoming digital audio. Input Frame Rate The frame rate of the received AES3 format data. Output Sample Rate (Fso) The sample rate of the outgoing digital audio. Output Frame Rate The frame rate of the transmitted AES3 format data. Dynamic Range The ratio of the maximum signal level to the noise floor. Total Harmonic Distortion and Noise The ratio of the noise and distortion to the test signal level. Normally referenced to 0 dBFS. Peak Idle Channel Noise Component With an all-zero input, what is the amplitude of the largest frequency component visible with a 16K point FFT. The value is in dB ratio to full-scale. Input Jitter Tolerance The amplitude of jitter on the AES3 stream, or in the ILRCK clock, that will cause measurable artifacts in the SRC output. Test signal is full scale 9 kHz, Fsi is 48 kHz, Fso is different 48 kHz, jitter is 2 kHz sinusoidal, and audio band white noise. AES3 Transmitter Output Jitter With a jitter free OMCK clock, what is the jitter added by the AES3 transmitter. Gain Error The difference in amplitude between the output and the input signal level, within the passband of the digital filter in the SRC.
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CS8420 18. PACKAGE DIMENSIONS 28L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1 b c D SEATING PLANE e A1 L A
INCHES DIM A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.697 0.291 0.040 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.713 0.299 0.060 0.419 0.050 8
MILLIMETERS MIN MAX 2.35 0.10 0.33 0.23 17.70 7.40 1.02 10.00 0.40 0 2.65 0.30 0.51 0.32 18.10 7.60 1.52 10.65 1.27 8
THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameter Junction to Ambient thermal impedance (28 pin SOIC) Allowable Junction Temperature Symbol JA TJ Min Typ 65 Max 135 Units C/W C
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CS8420 19. ORDERING INFORMATION
Product Description Package Pb-Free No CS8420 Digital Audio Sample 28-SOIC Rate Converter Grade Temp Range Container Rail Rail Rail Order# CS8420-CS CS8420-CSZ CS8420-DSZ Commercial -10 to +70C Commercial -10 to +70C Yes Automotive -40 to +85C CDB8420 Evaluation Board for CS8420 -
Tape and Reel CS8420-CSR Tape and Reel CS8420-CSZR Tape and Reel CS8420-DSZR CDB8420
20. REVISION HISTORY
Release
PP1 PP2 PP3 1st Preliminary Release 2nd Preliminary Release 3rd Preliminary Release -Added IS package to front page. -Added IS package to "Ambient Operating Temperature:" on page 6. -Corrected "Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK" on page 28. -Revised "SRC Invalid State" on page 49. -Added DS package to front page. -Added DS package to "Ambient Operating Temperature:" on page 6. -Corrected "tdpd" on page 9. -Corrected "tlmd" on page 9. -Corrected "tsmd" on page 9. -Corrected "tdh" on page 10. -Added "C/U Buffer Data Corruption" on page 49 -Added lead-free ordering information. Final Release 1 -Changed format of Figure 17 on page 20 and Figure 18 on page 21. -Changed SORES description to refer to sample rate converter as data source in "Serial Audio Output Port
Changes
PP4
PP5
PP6
F1
Data Format (06h)" on page 39.
-Added "Transmitter Startup" on page 48. -Integrated D1 Errata in Section 16.2 on page 87 .
F2
Final Release 2 -Updated Ordering Information. -Added "Block-Mode U-Data D-to-E Buffer Transfers" on page 50. Final Release 3 -Updated Ordering Information. Final Release 4 -Updated Leaded/Lead-Free information in "Ordering Information" on page 93.
F3 F4
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Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola Inc. AC-3 is a registered trademark of Dolby Laboratories, Inc. IC is a registered trademark of Philips Semiconductor.
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